EDN -- 04.25.96 VCO has digitally programmable center frequency

Design Ideas: April 25, 1996

VCO has digitally programmable center frequency

Paul Sofianos,
Motorola LICD, Chandler, AZ

Figure 1 illustrates a narrowband VCO, which has a digitally programmable center-frequency ratio of greater than 2-to-1. With a VCO having center-frequency ratio (F _HIGH/F_LOW) of greater than 2-to-1, you can derive any output frequency by simple binary division. The VCO has extremely high spectral purity, and typically operates at frequencies greater than 230 MHz by using high-performance ECL. Also, you can enable and disable the VCO almost instantaneously.

Many applications, such as clock recovery, require a narrowband VCO. However, if the fundamental clock frequency varies widely, the VCO must operate over a greater ratio. This greater ratio increases the radial gain constant (or input sensitivity in megahertz per volts), which negatively impacts the loop-filter response characteristics. Digitally resetting the center frequency preserves the narrowband nature of the VCO and still maintains a wide operating margin. Especially for clock-recovery circuits, the VCO must be capable of extremely fast enable and disable times.

Initially, you program the circuit to the desired center frequency by applying a digital value on the DATA_BUS. A logic high on the DATA_LATCH input latches that value into IC₁, a programmable-delay IC. Figure 2a shows a graph of the DATA_BUS input-value N vs center frequency for a typical design. With the VCO_ENABLE input at a logic low, the outputs of IC₂ and IC₃ (F_OUT) are also low. Pin 7 of IC₁ is high, forcing the output of IC₁ to a logic low.

Approximately 260 psec after the VCO_ENABLE input goes high, F_OUT goes high, which begins the output-frequency cycle. A high at F_OUT enables IC₁'s input, which is high. After the digitally programmed delay (Figure 2b), plus a delay value dependent upon V_VCO (Figure 2c), pin 14 of IC₁ goes high. This logic-high signal propagates through IC₂ and forces F_OUT back to a logic low, which disables IC₁.

Now, the entire cycle repeats itself until VCO_ENABLE goes back to a logic low. A low at VCO_ENABLE forces F_OUT back to a logic-low state within 500 psec. Therefore, with the aid of Figures 2b and 2c, you can express the frequency F_OUT as:

where T_pdd(IC₁) is the digital propagation delay of IC₁ that Figure 2b shows, T_pda(IC₁) is the analog (V_VCO) propagation delay of IC₁ that Figure 2c shows, T_pd(IC₂) is the propagation delay of IC₂, T_pdIC₃ is the propagation delay of IC₃, K is the propagation delay in psec due to trace lengths, and N is the DATA_BUS value.

For a typical layout, K is approximately 200, so:

Thus, for N=0, the center frequency is 231.7 MHz, and the VCO's tuning range is ±6.2 MHz. For N=127, the center frequency is 113.8 MHz, and the VCO's tuning range is ±1.5 MHz. R₁ through R₄ are standard ECL termination resistors. C₁ and C₂ bypass the V_VCO and V_BB voltages, respectively.