Design Ideas: April 25, 1996
Figure 1 protects CMOS interface circuitry by sensing excessive currents. IC1 monitors the supply current (IS) to the interface circuitry and quickly removes current and voltage from the interface if IS exceeds a programmed threshold. During normal operation, the current from IC1's Out terminal (1/2000 of IS) flows through R3 to a logic-low level: the output of IC2's lower NOR gate.
During a fault condition (defined as IS>-50 mA with the R3 value shown), the rising Out current develops 1.2V across R3, causing the set/reset flip-flop IC2 to produce a low-to-high transition at pin 4. This action shuts down the interface: Q1 blocks the interface supply current, and Q2 crowbars the interface supply to prevent overvoltage. Without the crowbar, an external overvoltage fault could act through the parasitic diodes in Q1 and the interface IC to raise the main supply voltage. (A positive supply voltage tends to rise if the load asks the supply to sink current.)
R3's connection to the flip-flop output instead of to ground (as in most circuits using the MAX471) introduces hysteresis in the control of Q1 and Q2. Without the hysteresis, oscillation can result: Turning off Q1 removes the fault current, and the circuit tries to resume normal operation. R2 and D1 provide a break-before-make action that prevents Q1 and Q2 from shorting the supply rails. Once tripped, the circuit remains latched until you reset it manually with S1.
You could connect an LED with a current-limiting resistor as a fault indicator between the main supply and the Q1-Q2 node. Other possible modifications include a capacitor across R3 to provide "slow-blow" action and the use of a precision reference and comparator for greater accuracy in sensing the R3 voltage. (DI #1864)