Design Ideas: April 25, 1996
Figure 1 expands a popular DSP chip's boot loader to load to 32k words of zero-wait-state memory from a slow EPROM. The chip then executes the program at full speed. After the boot-load process is complete, the routine releases the branch-testable input flag for use in general-purpose application-software.
TI's TMS320C26BFNL is a 16/32-bit DSP chip that can run at 10 MIPS. Accessible memory consists of three separate banks for program, data, and I/O spaces with interrupt service-jump vectors at the beginning of the program space. Setting the MP/MC pin determines whether the chip uses external program memory (µP mode) or internal-program ROM (µC mode). An internal ROM containing a boot loader uses the first 4k words of program memory in the mC mode. The 16-bit data bus normally requires two bytewide EPROMs, but in this case a pair of 32k38-bit static RAMS (<-40 nsec) replaces the EPROMs.
Holding the MP/MC pin low activates the internal boot-loader ROM. Shortly after reset, the boot code evaluates the basic-input-output (BIO) pin and two signature bytes mapped into global data space in the EPROM. Because the BIO is high and the first two bytes in the data EPROM are 0xFF and 0x80, the DSP chip transfers bytes stored first as high byte, then as low byte to the internal 16-bit RAM until the transfer causes filling in all 1568 words. After the transfer, the internal ROM jumps to this new program code and begins execution. The next step uses the boot-loaded code to initialize the external 32k-word RAM.
Listing 1 gives the program code. The code transfers bytes starting at the beginning of the application code in the EPROM to the program space-mapped RAM, for a total of almost 32k program words. After the EPROM address wraps past 0x7FFF, a dummy I/O-space read pulses the I/O-space select pin. This pulse sets address pin A15 in the EPROM and forces all further reads from the upper 32-kbyte bank. The pulse also allows the external BIO signal to pass to the DSP chip, instead of being held high. The last step the code takes is to branch to address 0x8000, where the application code now begins. Before enabling interrupts, the application code should reconfigure the internal program memory to data space and supply any necessary patches to the interrupt jump vectors at locations 0xFA02 through 0xFA0E.
This design is flexible and has many possible permutations. You can partially or totally disable the EPROM by setting the DSP chip's global data-memory register appropriately after boot loading. You could also use smaller external RAM or EPROM devices. You could modify the code in Listing 1 to download only the desired EPROM, and the code could leave the remaining data in the EPROM's upper 32-kbyte bank for look-up tables with single-wait-state access. You could also modify the code to map the EPROM code to a different RAM map. Instead of using the IS pin to generate the necessary pulse, you could use XF or DX pin. Finally, for holding larger tables or program overlays, you could use a larger EPROM with a more elaborate bank-switching technique, as opposed to using the address bit A15 and a single flip-flop. (DI #1859)