EDN -- 04.25.96 Philips enters the CPLD market

Out in Front: April 25, 1996

Philips enters the CPLD market

Philips Semiconductors is emerging as a new player in the expanding complex-PLD (CPLD) market. The company has formed a new business unit and strategy to develop and market 3.3V CPLDs for low-power and high-speed applications and 5V devices for portable applications. Two key technologies in Philips' CPLD development are the company's XPLA architecture and Fast Zero Power (FZP) design technique. XPLA combines PLDs and PALs on one device. The result is a highly flexible architecture that provides high design usability of a device's macrocell logic and 8-nsec, predictable pin-to-pin delay at 3.3V, no matter how many product terms you allocate to a design. The company's FZP technique results in low static and dynamic power. All members of the first two Philips CoolRunner families, the PZ5000 (5V) and PZ3000 (3V), have static power consumption less than 100 µA. Dynamic power at maximum operating frequency, greater than 100 MHz, is 50 mA. The company claims that spec is four to 20 times lower than the 200 to 1200 mA of other PLDs of comparable density.

Philips also offers software tools to help you implement your CoolRunner designs. For $95, you can buy a Windows-based tool that includes Boolean entry, simulation, static-timing analysis, and device compilation. In addition, the company has agreements with many EDA-tool vendors, including Cadence (San Jose, CA), Data I/O (Redmond, WA), Mentor Graphics (Wilsonville, OR), MINC (Colorado Springs, CO), Synopsys (Mountain View, CA), and Viewlogic (Marlborough, MA). These agreements allow you to use those companies' tools for design with Philips' CPLDs. The devices are available for sampling; production volumes will be available this year. The largest device contains 128 macrocells, equivalent to about 4000 logic gates. Philips is developing larger devices for release this year and in 1997.—by Jim Lipman

Philips Semiconductors, Albuquerque, NM. (505) 822-7196.