EDN -- 04.25.96 EDA tool offers early hardware/software-compatibility checking

Out in Front: April 25, 1996

EDA tool offers early hardware/software-compatibility checking

Version 1.4 of ArchGen from CAE Plus gives you a head start in validating software running on a chip's embedded hardware. You use the tool to generate an executable specification of the embedded system in C at the register-transfer level. You then validate the embedded system's software with this specification without a simulator at 100,000 cycles/sec or more. This method of validation is much faster than simulating the hardware with a hardware-description-language (HDL) simulator.

ArchGen lets you capture the embedded hardware specification both graphically and textually using C, Verilog, or VHDL. You validate the specification's functionality and performance with compiled embedded software, written in C or assembly code. Be-cause you verify system hardware before defining it at the gate level, you can explore alternative architectures, run system-feasibility tests, and optimize the hardware early in the design. You also save system-design time by developing IC hardware and application or embedded software in parallel.

You can translate ArchGen hardware models to RTL, VHDL, Verilog, or C. The VHDL and Verilog models are synthesizable, letting you direct the hardware to a target technology. ArchGen runs under Unix on Hewlett-Packard, IBM, and Sun systems. Prices are $79,000 for C-output and $69,900 for HDL-output capability. —by Jim Lipman

CAE Plus, Austin, TX. (512) 338-0165.