The Planet IC design-planning and analysis tool lets you perform fast calculations and what-if analyses before committing the design to silicon. The floorplanner obtains accurate estimations of a design's parasitics, timing, and area during the front-end-design or logic-synthesis process. Running on Sun and Hewlett-Packard workstations, the first release of Planet works with the vendor's IC-layout-tool, ArcCell-BV and costs $40,000 for a single license. Avant! Corp, Sunnyvale, CA. (408) 738-8881.

Software automates electrical-controls de-sign.

An integrated package of nine software modules aids productivity in electrical-controls design by creating accurate schematics, panel layout drawings, wire lists, and bills of materials. The software lets you read and write information to and from AutoCAD and programmable-logic-controller (PLC) software and pass information between documents. VIA Electrical Controls Design Software Version 4.0 consists of VIA schematic, VIA bill of materials, VIA panel layout, VIA file manager, VIA to-from, VIA renumber, VIA wire label, PLC-I/O libraries, and I/O documentation software interface. Prices range from $3500 to $5400 for Windows platforms. VIA Development Corp, Marion, IN. (317) 677-3232.

Integrated tools craft FPGAs.

The Galileo version 3.1 Time Explorer and Logic Explorer synthesis tools join Actel's Designer Series place-and-route software to optimize designs based on Actel's FPGAs. Time Explorer comes with a standard-delay-format (SDF) reader for post place-and-route timing analysis; expands VHDL Initiative Toward ASIC Libraries (Vital) back annotation for ACT 2, ACT 3, and the 1200XL Logic Integrator families; and includes a Boolean mapping algorithm for the 1200XL. Logic Ex-plorer lets you implement high-level datapath macro functions with its ModGen macro generator, which incorporates Actel-specific architecture information. Galileo prices start at $9000 for Windows 95 and NT and $13,000 for Sun and HP 700 Unix platforms. Exemplar Logic Inc, Alameda, CA. (510) 337-3700.

PC-board design tools check interconnections.

Two software packages, IS_Optimizer and IS_MultiBoard, provide interconnect synthesis of high-speed digital pc-board designs. IS_ Optimizer automatically optimizes routed net topologies according to specified timing and crosstalk requirements. IS_MultiBoard analyzes and verifies interconnect timing and signal quality of designs composed of multiple boards, multichip modules, connectors, and cables. Floating licenses for IS_Optimizer and IS_MultiBoard cost $25,000 and $15,000, respectively. Interconnectix, Portland, OR. (503) 684-6641.

Program manages circuit-simulation process.

MetaManager, a graphical management environment for the HSpice circuit simulator and the MetaCircuit timing simulator, reduces design- iteration times for IC development and timing simulation. MetaManager's library, design, stimulus, and analysis management functions result in a 5 to 10* improvement in iteration time over conventional solutions for cell, block, and custom chip designs. With its built-in waveform editor, MetaManager quickly sets up input stimuli for MetaCircuit and HSpice, creating single-transition, cycle-based-transition, and piecewise linear waveforms. Prices start at $10,000 for node-locked licenses. Meta-Software Inc, Campbell, CA. (408) 369-5400.

Synthesizable PCI core joins telecommunications library.

Featuring an optimized data path for zero-wait-state performance, a synthesizable 32-bit core transfers data at the maximum PCI-bus-system bandwidth. Part of the telecommunications segment of the Core_Lib family, the PCI core maintains the data and address context of each transaction. You can restart disconnected or retried transactions by activating the restart signal. Prices start at $42,000 for single-design use and $70,000 for unlimited-site license use, including VHDL source code. Technology Data Freeway, Concord, MA. (508) 371-9004.

Verilog simulator in- cludes built-in debugging.

Able to work at both the RTL and the gate level, the V-System/VLOG simulator adheres to the IEEE 1364 Verilog standard. The simulator permits interactive debugging with dynamically linked windows. A structure window displays a graphical view of the design hierarchy, and elements within the window can be expanded or compressed. You can select a design unit from within the structure window and automatically update the source and signal windows. A data-flow window shows how a signal traverses through the entire design hierarchy. V-System/VLOG costs $19,995 and runs on HP Series 700, SPARC, and IBM RISC System/6000 workstations. Model Technology Inc, Beaverton, OR. (503) 641-1340.

Updated simulator gains waveform analyzer.

Re-lease 4.6 of the System Hilo simulator adds the SimWave interactive waveform analyzer, enhances the software's dynamic timing analyzer, and increases support for Logic Modeling's ModelSource hardware-modeling family. SimWave provides triggering and waveform-editing functions and displays strobe failures, signal and event hazards, glitch events, and ambiguities. Hitime, System Hilo's dynamic timing analyzer, catches timing errors, such as spikes, in deep-submicron designs. Prices start at $20,000. VEDA Design Automation, Fareham, Hants, UK. (44) 1329 822240.