Design Feature: May 9, 1996

Low-voltage differential signaling (LVDS) IEEE-P1596.3 is a physical-layer, point-to-point interface that provides greater than 85-Mbps data transmission. LVDS is also extensible, because it allows power-supply voltages as low as 1.8V and is compatible with BiCMOS, CMOS, and GaAs.

LVDS uses two single-ended signals to create a differential signal (Figure 1). V_oAis the "true" signal, and V_oB is the "complement." The differential-signal equation shows that V_oD results from the subtraction of the complement from the true signal.

V_oD's low swing enables high-speed switching. Signals change a maximum of 400 mV and minimum of 250 mV centered at 1.2V from the driver ground. The less a voltage level has to change, the faster it can achieve the desired state. LVDS typically switches only 325 mV on each single-ended line.

However, data transfer is more than just switching transceivers. It also depends on system and protocol specifications. Typically, you can inexpensively build any system that requires 1-Gbyte/sec bandwidth and also has a 2-byte-wide data-transfer interconnect. Sampling at the Nyquist rate, the baud rate for such systems is 500 Mbaud, giving a 2-nsec bit width. The 2-nsec bit width must include the transition time, the time accounting for skew between parallel channels, and an interval at the stable voltage level to sample for data transfer.

Allowing 1/4 of the bit interval for transitions gives a total of 500 psec for the voltage to change a maximum 400 mV. This timing also ensures a good slew rate (10 to 90% signal change) of 0.8 V/nsec (400 mV/500 psec), which minimizes EMI or transmission-line problems. The fast slew rate is possible because of the low swing-voltage levels LVDS provides.

Low swing voltage at constant current lowers power demands in the total system. The low power consumption of LVDS gives a symmetrical operating margin between power rails to 2.4V. It also provides for lower power dissipation on chip, which enables semiconductor manufacturers to integrate transceivers directly onto the link-media-access portion of the interface. This feature saves board space and simplifies board manufacture.

Signal-and-noise effects

Digital system designers have to take noise into account. Power-supply noise in high-clock-rate, dense-component, digital systems can be as high as 250 mV p-p, even with good decoupling techniques. So you must account for the effects from noise in your design (Figure 2).

Interestingly, the minimum 250-mV differential signal of LVDS and the apparent lack of noise margin alarm some designers. However, the following noise analysis shows such fears are groundless.

You can divide noise in a system into two categories: common-mode and single-ended noise. Common-mode noise is seen by every component in the system, and single-ended noise is localized. Both noise types interfere with signals that are referenced to some voltage deemed stable. This stable voltage moves around with power supply and EMI-induced variations. With differential signals (Figure 2), the two single-ended signals move around in common with these variations. When the true signal is referenced to the complement, the common-mode variation between the two signals is zero.

The differential signal is immune to power supply and EMI noise when properly designed. Proper design for differential signals requires having each single-ended signal see the same common-mode voltage. The noise margin high (NMH) is the difference between the minimum driver-high-output voltage, V_{oh (min)}, and the maximum receiver-sensitivity-input high voltage, V_{ih (max)}:

NMH=V_{oh (min)} - V_{ih (max)}.

The noise margin low (NML) is relative to the other side:

NML=V_{il (min)} - V_{ol (max)}.

Equations 1 and 2 and the values in Figure 2 yield a 150-mV noise margin (both NMH and NML). Because this noise margin is immune to common-mode noise, it is acceptable for single-ended noise. Further, single-ended noise comes from transmission-line phenomenon such as reflections and crosstalk. You can minimize reflections by using the point-to-point transmission approach. The transmission path differential impedance can be perfectly matched with termination at the receiver output.

LVDS applications

One place where LVDS can prove useful is in attenuating the hardware and software bottlenecks that result from PC I/O data moving between expansion cards through the CPU. For example, National Semiconductor's QuickRing architecture accelerates data transfer by adding another bus to the PC architecture (Figure 3) allowing the data to bypass the I/O bus and CPU. This point-to-point architecture gives greater aggregate system bandwidth by freeing the I/O bus and CPU to perform other tasks.

In achieving this efficiency however, this new data bus should not generate noise or interfere with the existing components, space utilization, or power-supply generation and regulation. Perhaps most important, the new data bus must not add appreciably to the cost.

LVDS deals with this last requirement quite well. Conventional wisdom says that pins are expensive because of package size, manufacturability, and reliability, so one way to reduce costs is to reduce component pin count. Because LVDS can operate at a higher frequency, the data path can be narrower. Thus, fewer pins may be needed.

To address the noise and power-supply concerns, the IEEE-P1596.3 LVDS has three special features: First, the specification requires a frequency-independent constant-current driver; second, LVDS devices must operate in 5, 3.3, and even in future 1.8V systems; finally, the specification provides for low-voltage swings and differential signals that offer good electromagnetic compatibility features.

LVDS suits a wide range of other applications including telecommunications, data transmission, and computing. Currently telecommunications companies use EIA/TIA-422 to interconnect central offices and communication equipment. For example, EIA/TIA-422 specifies up to 10 Mbps transmission rate for a cable length of 10m, and LVDS delivers in excess of 100 Mbps.

LVDS' speed and power characteristics allow it to support numerous other applications, such as the asynchronous-transfer-mode ring networks, radio-wave transmissions, switching and data-acquisition systems, as well as satellite communications.

LVDS addresses all areas of concern for most high-data-rate applications, including bandwidth, power dissipation, reliability, and low noise emissions. With its capabilities, LVDS could be the next work-horse interface standard (Table 1).

Author's biography

William Chiang is a senior marketing director with National Semiconductor in Hong Kong. He holds a bachelor's degree from the University of Waterloo, Canada.

References

1. IEEE P1596.3/D1.0 Standard for LVDS (1994). IEEE Standards Department, 445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855.
2. "QR0001 QuickRing Data Stream Controller data sheet," National Semiconductor.