Out in Front: May 9, 1996
Compass Design Automation takes a new tack on the floorplanning design task. The company's enhanced ChipPlanner combines floorplanning with timing analysis and timing correction in one tool, reducing the number of iterations between floorplanning and synthesis. Previously, if you found a timing problem after floorplanning, you had to use separate tools to correct the problem. The new version of ChipPlanner integrates presynthesis, register-transfer-level (RTL) floorplanning with graphical timing tuning and analysis.
ChipPlanner lets you describe a VHDL or Verilog chip and perform a floorplan with mixed RTL and gate-level blocks and hard macros, such as memory arrays. ChipPlanner then translates the blocks into physical RTL models for presynthesis area, interblock-interconnect planning, and topology estimation. The tool reads the VHDL or Verilog description of each block and estimates the area required for structured logic, such as adders and multipliers, finite-state machines, and random-logic blocks. This feature provides a good estimate of internal block timing delays and path delays between blocks.
ChipPlanner has three new timing options: ShowTIME, a static-timing tool for timing estimation without using test vectors; FixTIME, which selectively resizes gates to meet timing specs; and MakeTIME, which prunes false paths and moves blocks to meet timing specifications. All three options use a common timing model to minimize inconsistencies among synthesis, timing analysis, and floorplanning.
ChipPlanner runs on Hewlett-Packard and Sun platforms. The tool's RTL-floorplanning capability will be in beta test in September. Beta versions of ShowTIME, FixTIME, and MakeTIME will be available in June, and production versions will be available in September. You can buy each as a separate option or all three with ChipPlanner for $110,000.
—by Jim Lipman
Compass Design Automation, San Jose, CA. (408) 433-4880