Out in Front: May 9, 1996
You can use Version 4 of Cypress Semiconductor's Warp2 design tool for any of the company's programmable-logic products: PLDs, complex PLDs, and FPGAs. Cypress has enhanced the tool's UltraGen synthesis capability, allowing Warp2's module-generation function to search VHDL source code for complex arithmetic and datapath operators and replace the operators with existing circuits optimized for the target programmable-logic family. UltraGen also lets you control synthesis on a block-by-block basis. Thus, you can optimize some blocks of a design for high speed and others in the same design for minimum area.
After synthesis, Warp2 generates timing-annotated VHDL- and Verilog-simulation models, which you can run on many popular simulators from Cadence (San Jose, CA), Mentor Graphics (Wilsonville, OR), Model Technology (Beaverton, OR), and Synopsys (Mountain View, CA). In addition, the tool has a built-in interactive functional simulator that lets you verify a design before programming the device. Warp2 also performs automatic fitting for all Cypress PLDs and CPLDs and automatic placement and routing for the company's FPGA devices.
Warp2 runs on Unix platforms from Sun and will be on Hewlett-Packard workstations in June. You can also get Windows 3.1, NT, and 95 versions. Any version costs $99.
—by Jim Lipman
Cypress Semiconductor, San Jose, CA. (408) 943-2600.