Graphical simulation environment mixes Verilog and VHDL.

SimVision, a graphical environment for the vendor's Verilog and VHDL logic simulators, offers a suite of advanced debugging and analysis tools and high-level design and visualization capabilities. Features include a bilingual source-code debugger, configurable hierarchical design and signal-flow browsers, and a customizable virtual-instrument display. Additionally, SimVision includes SimWave, a mixed-language, mixed-signal waveform editor from Systems Science. The software accepts industry-standard formats, such as TCL, PLI 2.0, and VCD, for viewing results of third-party tools. The SimVision environment comes with the Verilog-XL, NC-Verilog, and Leapfrog VHDL simulators. Cadence Design Systems Inc, San Jose, CA. (408) 943-1234.

EDA tool kits work with latest Xilinx FPGAs.

Updated device kits target the Xilinx XC5000 and XC4000F FPGA families with enhanced VHDL simulation and synthesis capabilities. Integrated into the vendor's design environment, each kit offers schematic symbols, simulation models, logic synthesis, and device-fitting technology. You can use X-BLOX elements in your Xilinx design, and the device kits let you run functional VHDL simulation before place and route. The kits also provide automatic inferencing of X-BLOX elements for VHDL synthesis. Upgrade pricing is $1000. Synario Design Automation, Redmond, WA. (206) 881-6444.

Software combo analyzes IC interconnects.

Version 3.2 of Raphael analyzes the effects of parasitic interconnect in ICs and can now be linked to the Dracula layout-parameter-extraction (LPE) tool from Cadence Design Systems. Because the LPE interface automatically generates the capacitance coefficients for the LPE rule deck, you do not need to worry about the correct syntax or correct mapping of these coefficients. With Raphael's updated graphical user interface, you can specify a stack of multiple dielectrics between any conducting layers by specifying the vertical position of those layers. Technology Modeling Associates Inc, Palo Alto, CA. (415) 856-8862.

Software translates net-lists from one HDL to another.

Three translators let you incorporate Verilog or VHDL designs into designs of the opposite language or reuse designs written in one language in a design written in the other language. Working at 5000 lpm, the unidirectional Verilog-to-VHDL, unidirectional VHDL-to-Verilog, and bidirectional hardware-description-language translators cover the synthesizable subset of Verilog and VHDL. The software translates module-by-module to maintain the design hierarchy. The V-to-V translators run on Hewlett-Packard and Sun workstations and cost $25,000 for unidirectional versions and $40,000 for the bidirectional. InterHDL Inc, Los Altos, CA. (415) 428-4200.

Software models radiated emissions.

Simulate radiated emissions and take corrective action early in the design cycle with REM software. The program lets you estimate the radiating currents flowing through your product's cables, connectors, and outside surfaces. The software obtains electric-field strength, radiated-power density, and magnetic fields at any frequency and distance from the device, which is modeled as a collection of radiating current elements. Calculated fields are presented as 3-D plots, 2-D polar and rectangular plots, or tabular data. REM runs on Macintosh and Windows PC platforms, with prices ranging from $780 to $3260. A Unix version is scheduled for the third quarter. RHR Laboratories, Richmond Hill, ON, Canada. (905) 884-2392.

Software cuts testbench-development time.

QuickBench automatically generates self-checking testbench models from intelligent timing diagrams. Based on the vendor's TimingDesigner, which automates timing-diagram generation and analysis, QuickBench produces VHDL and Verilog testbench models that you can use to verify designs during simulation. Models incorporate complex constructs, such as sampling, comparing, waiting for external events, and constraint checking. QuickBench, which runs on HP and Sun workstations and Windows PCs, costs $15,000. Chronology Corp, Redmond, WA. (206) 869-4227.

Software manages complex design projects.

Release 6.0 of the CMS product-data-management (PDM) program improves the software's productivity and extends its PDM capabilities for managing product life cycles, including CAD files, technical specifications, scanned images, product structures, and regulatory procedures. In addition, CMS 6.0 adds "parts," items that represent the part records in CMS. A vault server extends the CMS three-tiered architecture to include a server-based file vault that lets you localize vault spaces by creating vault servers at remote sites. A release management feature lets you control the state of an object at each revision level. CMS 6.0 costs $3095 per concurrent user and $595 per client, per concurrent user. Workgroup Technology Corp, Lexington, MA. (617) 674-2000.