Battery-operated portable equipment often makes use of the 80L51 µP's power-down mode to conserve battery energy. CMOS-memory contents are critical in many of these systems, so the system must sustain the CMOS-memory-supply voltage without interruption and for as long as possible.
In 
Figure 1, a µP supervisor (IC1) guards the µP (IC3) against brownouts and loss of power. When a declining battery voltage allows VCC to fall out of tolerance, IC1's LOWLINE output (pin 14) goes low and produces an interrupt that allows the 80L51 to initiate its shutdown routine. The contents of the RAM are unaffected as long as energy remains in the battery.
Without the AND gate, (IC2), IC1's RESET connects directly to RST on the 80L51. If the µP is in power-down mode and VCC falls below IC1's reset threshold, RESET goes high, causing the µP to shift from power-down to idle mode. As a result, the µP's maximum supply current jumps (according to its data sheet) from 100 µA to 6 mA. Battery voltage continues to fall and this condition persists until the battery discharges. The result is a much shorter backup time for the RAM.
The presence of the AND gate prevents the µP from this undesirable wake up. RST now remains low until you restore power by recharging or installing a fresh battery. RST goes high when VCC rises above the reset threshold in IC1. Thus, RST brings the 80L51 out of sleep mode only when VCC is valid.
When VCC is within the normal range, IC1's RESET is low and LOWLINE is high. If VCC falls below the lowline threshold (about 45 mV above the reset threshold), LOWLINE goes low and causes the 80L51 to begin its shutdown routine. If VCC continues to fall past the reset threshold, the AND gate blocks the resulting high RESET output.
The connection in Figure 1 also enables the µP to determine whether the battery voltage dips below the safe backup level at any time during the µP's sleep period. If so, the µP executes a "cold boot" because the power loss may have corrupted the CMOS RAM data. If not, the µP wakes up with a "warm boot" based on this data.
Specifically, IC1 includes a low-battery comparator that normally monitors the terminal voltage of a backup battery connected to BATT (this application has no backup battery.) The nonlatched comparator output appears at BATT OK. In the absence of an external connection, BATT senses the comparator output—which approximates VCC when high—through the 10k(ohm) resistor. This resistor also causes BATT OK to latch the state of BATT. A second connection to an available I/O line, that you would normally configure as a high-impedance input port, enables the µP to check the integrity of VCC and reset BATT OK when required.
If the battery voltage (VCC) goes below the BATT OK threshold of 2.25V, BATT OK goes low and drags BATT with it, latching both in the low state. Following a recharge or installation of a new battery, the µP then looks at the I/O line to determine how to restart itself. BATT OK high indicates a warm boot using the CMOS RAM contents. BATT OK low indicates a different routine: the µP initiates a cold boot, reconfigures the I/O line as an output, and sets this line high for about 30 µsec to latch the BATT OK output high again. Finally, the µP configures the I/O line as an input to resume monitoring the BATT OK output. (DI #1868)