EDN — 05.23.96 Verilog simulation gets a performance boost

Out in Front: May 23, 1996

Verilog simulation gets a performance boost

Viewlogic Systems has introduced a technology enhancement to accelerate VCS, the company's event-driven Verilog simulator. The new technology, called Roadrunner, combines features that speed both actual simulation and design-debugging time. You need not modify any models that run on VCS to run on Roadrunner.

You select two- or four-state simulation on a module-by-module basis, letting you use the slower and less memory-efficient four-state simulation only when you need it. Roadrunner's automatic design-abstraction capability also speeds simulation. The tool combines sequential-logic functions into a combinatorial-logic block. This feature allows you to simulate at a higher level of abstraction, reducing the number of events and speeding simulation. Throughout the process, Roadrunner maintains timing accuracy across the separate sequential-logic blocks. The tool also performs some logic minimization, reducing the number of logic gates to be simulated, again keeping timing accuracy intact.

During compilation, Roadrunner performs several optimizing operations. The optimization results in less procedure-call overhead and, thus, faster simulation. During debugging, you select the simulation detail for each module, choosing more detail for parts of the design exhibiting more problems. This feature results in faster simulation during debugging and a faster overall debugging cycle. Roadrunner is available as an option to the VCS 3.0 Verilog simulator. It will be available to beta customers in the third quarter for $30,000. VCS 3.0 costs $40,000 and currently runs on Unix platforms. The company is currently developing a Windows version of VCS.

—by Jim Lipman

Viewlogic Systems, Fremont, CA. (510) 659-4001.