EDN — 05.23.96 16-bit HC12 provides direct migration path for HC11

Out in Front: May 23, 1996

16-bit HC12 provides direct migration path for HC11

Motorola designers just gave the 8-bit HC11 architecture a complete redesign, turning the CPU into a 16-bit machine: the 68-HC12. The HC12, although a true 16-bit architecture, has the exact register set and interrupt stacking order as the popular HC11. In addition, the HC12's instructions are a superset of the HC11, making the HC12 100% upward-compatible with the HC11. To run your HC11 code on the HC12, you must account only for changes to timing loops, due to a clock-speed increase to 8 MHz, and shorter instruction-cycle times.

The HC12 uses a PLL to hit 8 MHz and to help with the CPU's power management. Current implementations of the core operate off voltages of 2.7 to 5.5V, with a path to 1.8V. The HC12's core has many other power-saving features. It also supports high-level languages better than the HC11 does. One reason is that the HC12 supports several indexed addressing modes, the most important of which is stack-pointer referencing to handle stack-based parameters. Auto-increment and decrement indexed addressing is useful for loop counters in C. You can use the HC12's load-effective address instruction in C programs to allocate and deallocate stack space. Indexed indirect addressing modes for case statements allow you to put a computed GOTO instruction in line.

A new division instruction lets the HC12 divide a 16-bit number by a 16-bit number instead of using a sign-extended 32-bit number. Furthermore, the HC12 performs this divide in 12 cycles, compared to 41 cycles for the HC11. Minimum/maximum functions compare two values and store the result in the accumulator or memory. For example, for a minimum function, the 湣 stores the smaller of the two values. Similar to the 68300 family, the HC12 performs table-look-up and -interpolate functions. These functions are useful for operations such as compressing table data. The HC12 also includes five instructions for fuzzy logic.

Motorola designers based the HC12 on a modular design methodology, similar to that of the 68HC16 and 68300 families. The design uses the Lite Module Bus, which is similar to the intermodule bus, to connect the core to peripheral modules. The HC12's core contains a module that includes a multiplexed or nonmultiplexed bus, runtime monitors, and a background-debug mode (BDM) feature. The runtime monitors include a watchdog timer, a clock monitor that uses an RC time constant to monitor the speed of the crystal, and a periodic interrupt timer.

The BDM is a single-wire implementation vs four wires on the HC16. BDM offers code patching and two hardware breakpoints, however, which are not on all HC12 derivatives. BDM also performs nonintrusive reads and writes to memory while the CPU runs at full speed; BDM accesses on-chip memory during CPU dead cycles. You can also use BDM to program the on-chip flash or EEPROM or to program the address comparators to set hardware breakpoints.

The first device in the HC12 family is the 68HC812A4. It contains 4 kbytes of EEPROM; 1 kbyte of SRAM; an eight-channel, 8-bit ADC; an eight-channel, 16-bit timer; serial communication interfaces; paging hardware to accommodate as much as 5 Mbytes of memory; seven programmable chip selects; and as many as 94 I/O pins. The A4 comes in a 112-pin TQFP and sells for $19 (samples). The next device, the 68HC912B32 contains 32 kbytes of flash; 768 bytes of EEPROM; 1 kbyte of SRAM; an eight-channel, 8-bit ADC; an eight-channel, 16-bit timer; a four-channel, 8-bit PWM; a byte-data-link communication J1850 multiplexing protocol; and 64 I/O pins. The B32 comes in an 80-pin QFP and sells for $20 to $25 (samples).

For development tools, Motorola offers the M68HC12A4EVB evaluation board with a serial debug interface and an assembler and debugger. About a dozen third-party vendors will also offer development support for the HC12.

—by Markus Levy

Motorola Inc, Austin, TX. (512) 891-2000.