Out in Front: June 6, 1996
To address the growing need for complex pc-board timing verification, Interconnectix has developed Tau, a symbolic timing-analysis tool. Tau uses the bus-functional behavior of ASICs, processors, and other VLSI components, along with their timing-related information, to determine critical pc-board timing paths and timing slack before component placement and routing.
With Tau, you input a circuit-netlist description and bus-functional timing models for the board ICs. These models have functional component-interface behavior and delay- and timing-constraint information. You can develop bus-functional models using a built-in spreadsheet interface and timing information from a component data book. Alternatively, you can use Chronology's (Redmond, WA) TimingDesigner tool for entering bus-functional information in a timing diagram. Chronology's Synchrony program also lets you access models from many IC vendors. With bus-functional models, you need not supply simulation vectors. This approach can better handle complex component interface behavior, such as read, write, and bus-arbitration cycles, than can static-timing analysis. Symbolic timing analysis also results in fewer false errors than does static-timing analysis on asynchronous and other complex systems.
Tau is part of Interconnectix's pc-board floorplanning-, optimizing-, and interconnect-synthesis tools. You can input netlist information to Tau directly from many popular third-party tools, including Cadence's (Chelmsford, MA) Concept, Mentor Graphics' (Wilsonville, OR) Design Architect, and Viewlogic's (Marlborough, MA) Viewdraw. Tau runs on Unix platforms from Hewlett-Packard and Sun. The tool will be available in the third quarter for $35,000.
—by Jim Lipman
Interconnectix, Portland, OR. (503) 684-6641, fax (503) 639-3469, http:www.icx.com.