The scheme in Figure 1 generates accurate and repeatable logic sequences—even in the presence of interrupt activity. Specifically, the circuit generates 16-bit logic sequences with a resolution of 100 nsec. This circuit's repeatability is an advantage compared with other sequence-generation methods. For example, one alternative to this circuit is to use a table of entries that denotes the required logic in the processor's memory. A program could then output these entries on a latch with the required delay times between the sequences. However, in a complex system with interrupt-driven functions, maintaining time repeatability of these logic sequences becomes very difficult.

The scheme in Figure 1 generates the sequences by coupling an external programmable timer (IC₂) to the bus-request (BR) signal of an ADSP-2101. The circuit also connects a latch, IC₁, to the system bus. The circuit shows only a single 8-bit latch. However, you can connect another 8-bit latch to the D₈ through D₁₅ data bits to get another 8 bits of logic states. The outputs of this latch provide the required logic sequences. This latch maps into the program memory of the processor. The timer also maps into the program memory at an address adjacent to the latch. A data table in the program memory is the source of the logic sequences as well as the associated time. Each program memory word is 24 bits wide. The upper 16 bits denote the logic level, and the lower 8 bits denote the time duration for these levels.

The DSP program reads each entry of the data table and outputs the words on the data bus, first to the timer and then to the latches during the next machine cycle. Writing a byte to the timer also generates the BR signal. The CLKOUT signal from the DSP (10 MHz for this system) clocks the timer. After the timer count elapses, the BR signal deactivates. The bus is now free for other activities. During the time when the external bus is granted, program execution still continues from the internal program memory, which for the ADSP-2101 is 2k words. This technique is not suitable for DSP systems that store the program in the external program memory.

The timing diagram in Figure 2 shows the circuit's relevant bus signals. The programmable timer (IC₂) requires two clock signals: RCK latches a count into the timer, and a pulse at CLOAD triggers the timer. IC3 generates data-strobe pulses for the latch as well as the timer. During machine-cycle 1, the program writes the 8-bit-timer count into the timer using the RCK input. This signal also resets a flip-flop to assert the BR signal. The circuit generates BR late in machine-cycle 1 so that the DSP recognizes BR in machine-cycle 2.

In machine-cycle 2, the program latches the waveform logic levels in IC₁. The latch pulse also triggers the timer (and CLOAD), which starts counting down the previously loaded count. From machine-cycle 3 on, the DSP gives away the bus, and any more external bus activity cannot occur until the timer expires and deactivates the BR signal.

The circuit achieves a resolution of 100 nsec on this 10-MHz system. Using a higher clock rate, the circuit achieves a finer resolution. Because it takes two machine cycles to trigger the timer, you should load the timer with a count of 255-N+2, where N is the required time duration for any logic sequence in multiples of 100 nsec. For a duration of 800 nsec, the loaded count should be 249.

Listing 1 is a sample program to generate the logic sequences. The variable DATA_TABLE marks the start of the program-memory area, containing the waveform sequence definitions. (DI #1877)

Listing 1—Logic-sequence generator