Out in Front: June 20, 1996
For high-speed and -density designs, the Actel A32200DX device accommodates datapath rates as high as 150 MHz and provides 2560 bits of true dual-port SRAM with a 5-nsec synchronous access time and a 10-nsec asynchronous access time. The embedded SRAM comes in 10 blocks that you can configure as 32×8- or 64×4-bit memories. They are suitable for 100-MHz FIFO devices and other high-speed applications.The new device can internally decode addresses or other data as wide as 35 bits in 7.5 nsec. Pin-to-pin decode time is 15 nsec. A selected-for-speed version of the device, the A32200DX-2, reduces the decode times to 5.5 and 11 nsec.
The antifuse-based FPGA also has six array clocks and JTAG 1149.1-compliant, boundary-scan test circuitry. The A32200DX has as many as 202 user I/O pins and is available now in 208-pin PQFP and 240-pin RQFP packages. It costs $225 (5000).
—by Doug Conner
Actel Corp, Sunnyvale, CA. (408) 739-1010, http://www.actel.com.