Out in Front: June 20, 1996
With Express Project Manager, you choose either a pc-board or a PLD. Project Manager then configures Express for the desired task. Express Entry lets you enter your pc-board or PLD design as a schematic, VHDL description, library of parameterized modules (LPM), or a combination of these representations. The tool also has an Electronic Design Interoperability Format (EDIF) schematic-read and -write capability, so you can migrate schematics and libraries to and from Mentor Graphics (Wilsonville, OR), Synario Design Automation (Redmond, WA), and Viewlogic (Marlborough, MA) tools. After PLD-design entry, you use Express Compiler to synthesize the design to a netlist for a target FPGA or CPLD architecture. During synthesis, you can specify modules of the design you want optimized for either area or speed. Express TestBench then simulates device design to verify correct operation. TestBench supports IEEE 1076 register-transfer-level behavioral debugging and VITAL (VHDL Initiative Toward ASIC Libraries) 3.0-compliant gate-level simulation. Express includes vendor libraries and synthesis models for many PLDs.
With Express, you target FPGA and CPLD families from Actel (Sunnyvale, CA), Altera (San Jose, CA), AMD (Sunnyvale, CA), Lattice (Hillsboro, OR), and Xilinx (San Jose, CA). Express interfaces to many vendors' back-end placement-and-routing tools, including Actel Designer Series, Altera MAX+PLUS II, AMD MACH-XL, Lattice pDS+, MINC (Colorado Springs, CO) PLDesigner-XL, and Xilinx XACTstep. OrCAD plans to ship Express in the fourth quarter for $4995. OrCAD's FPGA Designer Pack, which combines design-capture and -simulation tools costs $2995 until June 30, 1996, and $3995 until Sept 30, 1996. If you purchase it by Sept 30, you get a free upgrade to Express.
by Jim Lipman
OrCAD, Beaverton, OR. (503) 671-9500, fax (503) 671-9501, http://www.orcad.com.