EDN — 06.20.96 Electronic Design Automation

Electronic Design Automation: June 20, 1996

Software package eases MCM design.

A tool suite with common interfaces, Tanner Tools MCM Pro, provides schematic-capture, simulation, layout, verification, and signal-integrity analysis of multichip modules (MCMs). The software performs 3-D finite-element thermal analysis to determine optimal chip location before routing, as well as time-domain simulation using transmission lines and vias extracted from layout. The place-and-route tool places the die footprints, displays connectivity using a rat's nest, and provides auto-routing of die and pad interconnects. Tanner Tools MCM Pro runs on PC and Sun platforms, and prices start at $14,995. Tanner Research Inc, Pasadena, CA. (818) 792-3000.

Design-entry tools permit interoperability of editors.

Release 2.0 of the Active-CAD mixed-mode, design-entry platform provides direct interoperability among the vendor's schematic-capture, state-machine, and hardware-description-language editors. The tools run under Windows 3.11, 95, and NT. This version includes a revised project manager that merges the design editors, hierarchy browser, and error-message indicator into one window. Real-time cross-probing provides automatic back-annotation of design results between the schematic editor and gate-level simulator. Prices start at $1995 (end user). Aldec Inc, Henderson, NV. (702) 456-1222.

RF-design software simulates nonlinear circuits.

A high-frequency version of Spectre/XL for RF and microwave design provides interactive simulation of nonlinear communications circuits, such as mixers and receivers. The calculation of phase noise extends Spectre/XL's ability to quickly simulate the resonant frequency and harmonic content of oscillator circuits. For mixers, the program finds conversion gain, optimal local-oscillator power, and gain compression as RF power is swept. Amplifier analysis includes single-tone gain compression, power-added efficiency, harmonic products and distortion, intermodulation products, and the third-order intercept point. The PC-based software costs $1795. Avista Design Systems, Folsom, CA. (916) 985-6080.

Variable-die layout tool performs line-probe routing.

The SonIC V2 is more efficient than either channel or maze-based routers. The device provides line-probe-area routing for five layers of variable-die-structured custom ASIC and microprocessor layouts. SonIC V2's line-probe-routing algorithm estimates the area needed in the channels between rows of cells, enabling the device to produce very compact standard cell ASICs. SonIC V2 handles top-level layout of mixed blocks and cells, including nonrectangular blocks. The system costs $240,000. Silicon Valley Research Inc, Mountain View, CA. (415) 962-3000.

Signal-integrity simulator considers imperfect ground effects.

The ContecOmni simulator for Sun and HP workstations analyzes signal traces with split power planes; power and ground planes with holes, slits, and cutouts; and power and ground islands. Contec-Omni uses CAD database-conversion routines and special field solvers to acc- urately account for these imperfections, which ad-versely impact signal quality and EMI. Contec-Omni interfaces with Cadence's Allegro and Mentor Graphics' Board/MCM Station. Prices start at $60,000. Contec CAE Ltd, San Jose, CA. (408) 434-6767.

Program boosts IC layout-conversion speed.

Using a 30% faster compaction algorithm, V2.1 of the Layout Conversion Environment (LACE) improves IC layout-conversion speed, memory utilization, and usability. For example, circuits that are 50% larger are converted with no increase in memory. With LACE 2.1, IC layout conversions take one to two weeks to set up and 20 hours of CPU time to automatically convert a typical 50,000-transistor design on a Sun SPARC 20 workstation. In comparison, manual conversions would take several man months. Prices start at $250,000. Rubicad Corp, San Jose, CA. (408) 995-3334.

Netlist-conversion service handles unsimulated ASICs.

Orbit Semiconductor is expanding its Encore! FPGA-to-gate-array conversion program to include ASICs that have never been simulated and have no test vectors for design-conversion verification. The first phase of the "no-vectors" program covers the Xilinx 3000 and 4000 series FPGAs and the Advanced Micro Devices Mach and PAL series chips. NRE charges range from $13,000 to $25,000, based on gate count (300 to 45,000 gates). Orbit Semiconductor Inc, Sunnyvale, CA. (408) 744-1800.

Netlist translator im-proves property mapping.

Handling multiple formats through optional add-ons, the Omninet netlist translator lets you look at property names and read many varieties of EDIF files. The device offers a user-definable setup file that allows full customization for automatic name checking and substitutions. The software runs under Unix, DOS, and Windows 3.x, 95, and NT. Prices start at $395. Router Solutions Inc, Newport Beach, CA. (714) 721-1017.