Out in Front: July 4, 1996

IBM continues to proliferate its 401 product family with the introduction of the 401GF. Similar to the other family members, the 401GF is PowerPC instruction-set-compatible, has a three-stage execution pipeline, hardware multiply and divide, and static-branch-prediction support. The 401GF differentiates itself from the other 401 products by concentrating on low power and low cost. At 2.4V, the GF operates at 25 MHz and consumes 40 mW typical and 0.015 mW in sleep mode.

The 401GF achieves its low cost of $13 (10,000) by using a multiplexed address/data bus that helps the device fit into an 80-pin TQFP. To further reduce costs, IBM removed the GF's DRAM controller, DMA units, and serial port. The 401GF still has a 2-kbyte instruction cache and 1-kbyte data cache, common to the other 401 devices. The GF also includes an external bus controller that supports burst mode for filling a 16-byte cache line, fixed and programmable timers, a watchdog timer, and JTAG support. The chip's JTAG interface works with IBM's RISC-Watch debugging tool, which provides a ROM monitor, trace debugging, and similar functions. IBM also offers an evaluation kit that includes a board, compiler, and debugging support.

—by Markus Levy

IBM Microelectronics Inc, Mount Prospect, IL. (800) 426-0181, ext 555.