EDN — 07.04.96 PC-based FPGA/CPLD synthesis tool is PC-based

Out in Front: July 4, 1996

PC-based FPGA/CPLD synthesis tool is PC-based

FPGA Express, Synopsys' first Windows-based tool for programmable-logic design aims at high-density FPGA and complex-PLD (CPLD) chips. The tool uses a Verilog or VHDL design description at the register-transfer level (RTL) instead of traditional schematic input and synthesizes a gate-level representation of the design. Synopsys claims a chip area and performance improvement as high as 25 percent over what you can get with existing PC-based FPGA/CPLD-synthesis tools for devices with as many as 100,000 gates.

Using FPGA Express, you first select a design for synthesis. You then select the target vendor and device from a menu and specify design timing requirements and constraints, including both internal delays and external system parameters, such as input setup times and clock frequency. The tool then optimizes the design to a gate-level representation for the chosen target device. FPGA Express automatically generates modules for various hardware-description-language (HDL) operators, such as adders and counters, which it optimizes for the selected device architecture. The tool supports both Electronic Design Interchange Format (EDIF) and Xilinx Netlist Format (XNF) files, letting you perform mixed-VHDL-, Verilog-, and schematic-design entry. You can simulate a gate-level design using a third-party simulator before placing and routing the design with an FPGA/CPLD place-and-route tool.

FPGA Express has links to back-end design tools from Actel (Sunnyvale, CA), Altera (San Jose, CA), Lucent (Allentown, PA), and Xilinx (San Jose, CA). It also supports FPGAs and CPLDs from those companies. Xilinx support will be available in September, and Synopsys will add support for the other vendors over the succeeding months. The tool runs on Windows NT and 95. Prices start at $12,000, including the base system for either VHDL or Verilog and an architecture-specific optimization and interface module for devices from a single vendor. The other HDL-synthesis module, for mixed VHDL/Verilog-design entry, costs $4000 extra, and additional vendor-specific-optimization and interface modules cost $4000 each. An on-line VHDL training class costs $1000.

—by Jim Lipman

Synopsys, Mountain View, CA. (415) 962-5000, fax (415) 965-8637, http://www.synopsys.com..