Out in Front: July 4, 1996
Sand's USB Device Controller (UDC) and USB simulation model are both available in Verilog and VHDL. The UDC connects the USB and an 8-bit device bus. The controller's core contains a digital PLL block to extract clock and data information from the USB, a serial interface engine to run the front-end USB functions, and a bridge-layer block to handle error recovery and various control functions. The behavioral simulation model lets you simulate host and control devices with high- and low-level command sets. The model contains a host submodel to simulate transactions that a USB host controller initiates, a device submodel to simulate a USB device, and a monitor submodel for logging and protocol monitoring. UDC core licenses are available now starting at $90,000. The simulation model costs $20,000.
Virtual Chips' four synthesizable cores are available in VHDL or Verilog and a test environment. The cores include a host controller/root hub, hub/function, and two types of function interfaces. The host/root core connects to the PCI bus and controls other devices on the USB. You use the hub/function core between the host and function devices as a "repeater," reducing
the number of peripheral devices that connect directly to the com-puter. You use one of the function cores for basic interface devices, such as mice or joysticks, and the other for telephony devices, printers, and external storage peripherals. The function cores and the test environment are available now for early adopter use and will be in production in the third quarter. The host/ root and hub/function cores will be available in the third quarter. Core prices start at $50,000, depending on configuration.
by Jim Lipman
Sand Microelectronics, Santa Clara, CA. (408) 235-8600, fax (408) 235-8601..
Virtual Chips, San Jose, CA. (408) 452-1600, fax (408) 452-0952..