Editorial: July 18, 1996

I'm sitting at a subterranean snack bar in the Las Vegas Convention Center during this year's Design Automation Conference (DAC). My jaw is on the table, and my eyes are bulging out, because everything I knew—and everything you know—about logic design has just crumbled to dust. Stan Chapski, president of ASIC-design consulting firm Arisix (San Jose, CA), has just told me that logic design with deep-submicron silicon doesn't work the way IC logic has worked for the past 25 years. It doesn't work the same way that RTL, DTL, TTL, LSTTL, STTL, ASTTL, ALSTTL, CMOS, advanced CMOS, F series, or any other logic family invented to date has worked.

For the past two years in EDN, we've been telling you that deep-submicron design presents many new problems. Timing simulators, long based on many assumptions that they are valid down to 0.5 µm, start to fall apart at smaller geometries. OK, so you need better simulators. EDA companies can build better simulators. We told you that below 0.5 µm, wire delay starts to dominate circuit timing and that transistor delay becomes less important. So, you have to be more careful with floor-planning and keep critical nets short. These are the problems with deep-submicron design that you should already know about.

What you probably don't know is that below 0.5 µm, flip-flops might just stop working! That's the news I heard from Chapski at DAC that blew me away. Chapski discovered this problem while migrating existing designs to newer ASIC processes for customers. Timing problems with the chips surfaced. Conventional timing simulation didn't indicate a problem, but microprobing the chips revealed the problem nevertheless.

Chapski then tried a more advanced timing simulator, Epilog, from next-door neighbor NextWave (San Jose, CA). Epilog confirmed what the wafer prober had already revealed. Even the short feedback path created by tying a D flip-flop's Q* output to its input can introduce enough delay to violate the flip-flop's input-hold time at the ASIC's maximum clock speed. For those of you following closely, that's the stereotypical divide-by-two circuit. If you violate the hold time, the flip-flop won't toggle reliably when you clock it. And, of the hundreds or thousands of such circuits you might have in your million-gate ASIC, one or two might not work. Ditto for shift registers.

This situation presents you with hard questions to ask of your EDA and ASIC vendors. If they haven't seen this problem yet, they will. Now is the time to decide what you are going to do to prevent these problems from invading your silicon. Of course, as this problem becomes more common, the vendors will develop effective remedies. Just make sure they don't learn on your next ASIC design.

PS: Once we get this problem solved and move to 0.1 µm, we'll face a whole new set of problems, because there won't be enough electrons to form a current with a statistical behavior.

Steven H. Leibson
Editor in Chief