Design Feature: July 18, 1996

Low-swing I/O circuits, with their low noise margins, present a significant challenge to system designers. The list of proliferating low-swing I/O-logic families includes GTL (Gunning transceiver logic), GTL+, PECL (positive or pseudo ECL), LVDS (low-voltage differential signaling), and HSTL (high-speed transceiver logic) (Reference 1). Combining any of these logic families with CMOS circuits places conflicting demands on system design. CMOS circuits generate and tolerate high levels of noise, but the low noise margins of low-swing circuits are vulnerable to noise generated by their CMOS neighbors.

Fortunately, you can apply the same signal-integrity principles developed by the pioneers of mainframe computing to today's PC and server designs. Careful attention to a detailed noise budget (Reference 2) can ensure reliable system operation and immunity to dreaded intermittent noise faults. Even though the noise-budget approach requires a great deal of work and is susceptible to creeping conservatism, a noise budget is a valuable resource for making critical design decisions. The real trick is to make an accurate assessment of worst-case conditions without being restrictively conservative. You need to temper your noise budget with a consideration of the simultaneity of noise events.

The GTL bus serves as a good example for noise-budget analysis. GTL circuits are significantly different from their CMOS and low-voltage TTL (Table 1) predecessors. CMOS circuits generate and tolerate much higher levels of noise than do GTL circuits. For example, CMOS can tolerate 2V spikes on the pc-power distribution of a functional CMOS system. CMOS can withstand this level of noise, especially with large timing margins. However, try putting 2V of ac noise on the termination voltage bus of a 1.5V GTL system, and you'll spend a lot of time behind the scope probe.

To understand the sensitivity of GTL circuits to noise from their CMOS neighbors, you need to take a look at the circuits themselves. Then, you can develop noise budgets for the signal and power domains. For the purposes of this noise-budget analysis, the terms "GTL" and "GTL+" are interchangeable. The original implementation of GTL used a termination voltage (V_TT) of 1.25V and lacked sufficient noise margin. The GTL+ specification issued by Intel for the Pentium Pro microprocessor uses a V_TT of 1.5V.

One of the most important characteristics of a robust bus driver circuit is its output impedance. Z_OUT must be low enough for the device to drive the heavy capacitive loads encountered in a bus environment. Like its bipolar ECL predecessor, GTL meets this requirement, and it does so without excessive di/dt. You still need to pay close attention to simultaneously switching-output (SSO) noise, as you do with CMOS. However, for the same di/dt, the output impedance is much lower. Thus, you can switch all the loads on the first pass of the wave front instead of having to wait for the reflected wave, as in a CMOS bus.

Another benefit of GTL is the lack of overshoot and undershoot. With CMOS drivers, you find yourself trying to match the output impedance of the driver to the transmission line, so that the voltage steps up to half of V_DD at the driver and all the way to V_DD at the receiver. Variations in process and operating conditions can disturb this balance, causing nasty reflections that wreak havoc on signal integrity. Also, counting on ESD-protection diodes to clamp reflections at a safe level isn't always a good idea. For example, if you try using ESD-protection diodes as clamps with a DRAM load, you risk upsetting the charge pump used to bias the substrate and flipping a memory cell.

Figure 1 illustrates the differences between CMOS and GTL waveforms. The voltage scales are the same on these two plots; note the difference in signal swings. The CMOS waveform (Figure 1a) has more ringing than you would expect to see in a well-designed CMOS driver. (This driver simply consists of two inverter stages that were connected without much thought about slew-rate control.) However, this waveform does illustrate reflected-wave switching and problems with overshoot and undershoot. GTL drivers have the same vulnerability to package inductance; note the hint of ringing on the GTL rising edge (Figure 1b). Like any high-speed I/O circuit, GTL devices certainly fare better in a low-inductance package, such as the electrically enhanced plastic ball-grid array from LSI Logic (Fremont, CA).

Because most of the power dissipates in the off-chip termination resistors, GTL drivers also have the benefit of low on-chip power. However, these drivers do sink a lot of V_TT current, sometimes as much as 3A for a 64-bit bus.

Figure 2 shows the essential difference between 3.3V CMOS (or low-voltage TTL) and GTL noise margins. V_DD and the input threshold of the receiver dictate CMOS noise margins because the CMOS output stage alternately pulls the output all the way to V_DD and V_SS (Figure 3a). Alternatively, GTL uses an open-drain output stage (Figure 3b). The termination voltage defines the high level, and the combination of the output impedance and the termination resistance sets the low level. For its input stage, GTL uses a differential amplifier consisting of MOS devices. One pin on the receiver connects to the signal, and the complementary pin connects to a reference voltage, V_REF. Therefore, the termination voltage (V_TT=1.5V), the reference voltage (V_REF=2/3×V_TT), and the low-level output voltage (V_OL) define GTL noise margins.

The GTL bus terminates on both ends into its effective characteristic impedance, Z_OEFF, which is equal to the transmission-line impedance lowered by regularly spaced capacitive loads (Figure 4). In the case of a GTL bus, you can assume an ideal transmission line of inductance per unit length, L_O; capacitance per unit length, C_O; and regularly spaced capacitive loads, C_LOAD. Then,

A lower Z_OEFF means a lower termination resistance (RTERM), a higher V_OL, and lower noise margins.

You should now realize that there is not much room in GTL noise margins for a lot of CMOS-induced noise in addition to all other possible signal pathologies. In a utopian world, you could run a Monte Carlo simulation of every I/O circuit on every net (including the power distribution) across variations in manufacturing, operating conditions, and data patterns. Naturally, the computer capable of running these calculations has not yet been designed and will always be years ahead of those being designed today. A more practical approach is necessary to establish reasonable confidence in a design's noise immunity.

Creating the noise budget

A good place to start generating a signal-noise budget is to make a list of all possible signal pathologies that consume noise margins and to assign a numerical value to each one. Table 2 is such a list and includes the following: V_REF tolerance, dc drop, attenuation, reflections, SSO noise, and crosstalk. Not all of these may impact your system design. However, you should consider each one when you don't yet know which will be important to your application.

Theoretically, the sum of these noise-source values should be less than the dc noise margins of the driver and receiver of interest. What you typically find the first time you try to calculate this sum—and it's a lot of work—is that your chances of designing a functional computer are rather slim. Obviously, engineers design functional computers all the time, so there must be something missing. First, you have to go through the calculations for each entry in Table 1 to arrive at accurate values.

Incidentally, there is a temptation to apply the ever-popular root-sum-square to ac noise sources when the linear sum of the noise components exceeds the allowable budget. However, there is no convincing argument for this practice. Yes, root-sum-square is an accurate technique for combining the amplitudes of statistically independent probability functions. You might use such a technique when accounting for random thermal noise at the input of a high-gain amplifier. However, there are no random signal pathologies in a synchronous digital computer. They look random only because no mechanism exists to keep track of them all. And, if it's true that certain noise sources combine by superposition, then you can bet that, among the millions of clock cycles of data patterns, one exists that exercises this combination.

The first item in the signal-noise budget is the tolerance of the reference voltage, V_REF. This noise component is especially critical because the reference voltage is the standard by which the system judges ones and zeros. The voltage divider that creates V_REF (Figure 5) should be stiff enough to source tens of microamps without changing its voltage more than 1%. This requirement means using sufficiently small resistors. Furthermore, you should choose resistors with a low tolerance to minimize the effects on the noise margin. The following equation for V_REF assumes 2% resistors with one going to its high extreme and the other going low:

The next noise component is equally simple. The dc drop is just the voltage created by driver current's flowing through the resistance of a pc-board copper trace. The resistivity of copper is sometimes listed as 1.771 µ(ohm)-cm at 20°C (Reference 3), but Reference 4 lists a more convenient formula for use with pc-board traces. This example of a generic GTL bus assumes a 5-mil trace in 1-oz copper (1.4 mil) with a run of 12 in.

Using the equation from Reference 4, for a trace of width (w) and thickness (t),

Then,

The factor of 0.5 accounts for the fact that the current leaves the driver and splits. Half goes to one termination resistor and half, to the other resistor. As with many signal pathologies, the dc drop is negligible in standard CMOS and TTL circuits. In the case of GTL, 28 mV represents 7% of the 0.4V high noise margin, which is worth concern.

DC drop is easy to observe in simulation if you include R along with L and C in your discrete transmission-line model. If you want to do a simulation using the most realistic transmission-line model, you have to use a program such as ContecSpice from Contec USA (San Jose, CA) or XTK from Quad Design Technology (Camarillo, CA). Because these programs compute only the current and voltage at the beginning and end of the line and can include the effects of lossy components, the resultant transmission-line models are more computationally efficient and more accurate than standard Spice simulators.

Attenuation is a phenomenon that only microwave designers had to worry about in the past. This problem now creep ups in digital systems that include long cables and very high-frequency pc boards. The real culprit behind signal attenuation is skin effect.

Skin effect's physical origins are electromagnetic radi-ation on the surface of a conductor. As the electric and magnetic fields interact with the atoms in the conductor, the fields lose energy. "Skin depth" is the depth at which the amplitude of the fields drops off to 1/e of their original amplitude. When the wave front travels parallel to the axis of the transmission line, the skin effect pushes the current toward the edges of the conductor, thereby increasing the effective resistance.

Alpha is the fraction of the signal amplitude at the far end of a transmission line after attenuation takes its toll. The following equation results when you solve the coupled partial differential equations for voltage and current as a function of time and distance along a transmission line:

The definition of alpha is for a small-signal sine wave of frequency (f) traveling down the transmission medium. You can analyze trapezoidal signals as a combination of sine waves of different frequencies, amplitudes, and phase relationships. Attenuation of the fundamental frequency causes decreased signal amplitude. Attenuation of the higher order harmonics causes the edges to roll off. The current example assumes a 50-MHz data signal (100-MHz clock) and includes only amplitude degradation.

The equation for alpha includes three variables: the effective impedance of the transmission line, Z_OEFF; the trace length, l; and the resistance per unit length, R. The pc-board portion of the load includes the stub, vias, land pad, and, possibly, a connector. The IC portion of the load includes the package, bond pad, ESD devices, and output devices.

The resistance actually consists of two components: ohmic and skin-effect resistance. You can calculate the skin-effect resistance as follows:

To combine the effects of ohmic and skin-effect resistance, calculate

For this example, then, the final attenuation, a, and corresponding Va are

and

where Va is the amount of attenuation of the original signal.

Signal-noise budget: reflections

Impedance discontinuities cause reflections. You can calculate the effect of reflections using the same math when you solve the differential equations for a wave on a string. When the wave encounters a region of string where the mass density changes, some of the energy travels across the boundary between the two regions and some of it reflects back into the first region. The characteristic impedance of the two regions determines the amount of reflected energy.

The electrical analogs to the mechanical system's two regions of string are the following two impedances: Z_OEFF, of the transmission line, and the termination resistance, R_TERM. The following equation for the reflection coefficient, (rho), assumes a 5% variation in R_TERM and a 10% variation in ZOEFF:

To get the size of the reflection, you multiply (rho) by the amplitude:

(These equations account only for reflections resulting from the mismatch of Z_OEFF and R_TERM. They do not account for reflections that result from unevenly distributed loads.)

Signal-noise budget: SSO noise

SSO noise is often the single biggest hitter in the noise budget; this noise is also easy to overestimate. Faraday's Law says that a changing magnetic flux (from a changing current) creates a voltage across the flux loop that is proportional to the time derivative of the flux. The constant of proportionality happens to be the inductance of the flux loop. In the case of SSO noise, the current comes from a switching driver, and the inductance comes from a signal pin and its return path. The effect is a blip on the on-chip power and ground buses.

This blip eventually couples into the output signal and becomes a noise-margin problem. (This blip finds its way onto the power planes of the pc board, as well.) The best way to observe SSO noise is to measure its effects on a nonswitching (quiet) signal at the receiver, because the receiver's dc-transfer curve defines the noise margins. The amplitude of the noise at the receiver is the actual number you use in the noise budget. SSO noise may not necessarily affect switching and nonswitching signals in the same way.

SSO noise is a function of the driver di/dt, package-inductance L, the number of outputs switching per ground pin N, and the routing skew-coefficient K (data and clock), as follows:

The routing skew-coefficient K is intended to account for variations in phase between simultaneously switching drivers. Clock and routing skew work in favor of lower SSO noise. In general, the SSO noise amplitude is not as high as if you artificially forced all outputs to line up at the same instant. Because SSO noise prediction is such an involved topic and you don't have the information necessary to develop an SSO model unless you designed the chip, it would make sense for IC vendors to provide a worst-case SSO number in a data book (see box, "Soapbox: Make data books useful and models available").

When calculating ground or power inductance, remember that a loop is necessary to form an inductance. The signal and ground leads that supply the signal current form the current loop in question. The farther the signal and ground leads are from each other, the larger the loop area and the greater the inductance. Every signal lead in a package has a different inductance to the same ground lead by virtue of its position relative to the ground lead.

An accurate model of SSO noise requires considering a variety of effects (Figure 6). For example, the model must have a correct input edge rate, because the input edge rate affects the output edge rate and di/dt. Thus, Figure 6's model includes internal buffers to model a realistic edge rate. Also, the CMET capacitor models the chip's interconnect metal between the buffers. CPAD models the capacitance of the bond pad. The package Rs, Ls, and Cs and ESD diodes act to load the driver down, so they affect di/dt, as well. When you run the simulation, make sure the driver's transmission-line load is realistic.

Signal-noise budget: crosstalk

As with SSO noise, you can quantify the amount of crosstalk by its effects on a quiet signal. The quiet line is sometimes known as the "victim" and its switching neighbors as the "aggressors." Crosstalk comes in two varieties: forward and reverse. Forward crosstalk travels along the neighboring conductor in the same direction as the wave that caused the crosstalk. Reverse crosstalk travels in the opposite direction.

Crosstalk has two mechanisms: inductive coupling (from magnetic fields) and capacitive coupling (from electric fields). In the strip line in Figure 7, inductive and capacitive crosstalk cancel in the forward direction but not in the reverse direction. In microstrip transmission lines, you need to worry about both forward and reverse crosstalk. The best way to quantify crosstalk is with a 2-D boundary-element field solver, such as Contec RLGC. Entering the structure of Figure 7 into this field solver results in a pc-board crosstalk number of 40 mV in Table 2. You can use such a package to experiment with various geometries until you find a ZO and crosstalk that meet your requirements. The main point is that you need to keep GTL traces farther away from other traces than you would with CMOS traces.

Package crosstalk may be a concern, depending on edge rates and package size. For faster edge rates, a greater percentage of the rise time is spent in the package, and a greater amount of the total energy couples into the victim signal. Using some simple assumptions, the following equation shows that package crosstalk can be a concern. These assumptions are: that the primary mechanism is inductive, that the signal lead has a self inductance of 10 nH, and that the mutual inductance (K_M) is 25% of the self-inductance. A self-inductance of 25% may or may not be a realistic number; ask your component or package vendor.

Package parasitics are difficult to model. You need a good 3-D field solver and a sophisticated lab to verify your models. Unless you're in the business of doing this for a living, you probably have to rely on your vendor for this data.

Connector crosstalk can be a significant effect in a backplane environment.

where K_XTALK is the crosstalk coefficient, which represents the percentage of the full voltage swing that couples into a neighboring line, and (Delta)V is the full swing of the aggressor signal.

Again, modeling the parasitic elements of a 3-D structure from an electromagnetic perspective is difficult. Fortunately, connector vendors, such as Robinson Nugent (New Albany, IN), Amp (Harrisburg, PA), and Burndy (Manchester, NH), are good about characterizing their components and providing you with a report. The vendors usually quote crosstalk as a percentage of the total voltage swing for a given edge rate.

Creating a power budget

In the same way that you generate a signal-noise budget (Table 2), you can also develop a power noise budget (Table 3). If you keep power-supply variations within the limits specified by the component manufacturer, then you can be assured that the dc noise-margin specifications will hold. Like the signal-noise budget, the power-supply-noise budget includes both dc and ac effects. Of these, the ac noise arising from bulk and high-frequency decoupling is most significant. If these two noise sources get out of control, they can combine with signal-noise pathologies to create the worst kind of data error: one that happens intermittently under unpredictable operating conditions and data patterns.

Power-noise budget: V_TT tolerance

The first item in the power-noise budget is the tolerance of the termination voltage. A linear regulator usually generates V_TT. These regulators typically have excellent noise and regulation specifications and are usually not a problem in GTL systems. Line regulation is the derivative of the output voltage with respect to the input voltage (0.5% for Linear Technology's LT1085). Load regulation is the derivative of the output voltage with respect to the output current (also 0.5%). Thermal regulation is the derivative of the output voltage with respect to the temperature (0.1%, assuming a 5W power fluctuation). The total of all these effects on a 1.5V supply is 16.5 mV.

Power-noise budget: voltage gradient

Voltage gradient is analogous to signal dc drop in the power domain. Consider an 8×8-in. pc-board on which four ICs each draw 2.5A from the far end. The amount of voltage gradient in this scenario is very low and does not pose a problem. However, if you use ICs that consume large quantities of current (such as the Pentium Pro microprocessor) or if you place a lot of high-current daughtercards on a backplane, you may need to worry about voltage gradient. At the very least, you should try to obtain an order-of-magnitude estimate. Anything more accurate than this estimate is hard to achieve, because you may have to perform a 2-D simulation of current flow vs location of loads. There are software packages and consultants to aid in this task from companies such as Amp Packaging Systems (Round Rock, TX).

You can calculate the voltage gradient, as follows:

and

where N equals the number of ICs, I equals the current from each IC, and l is the length.

Power-supply decoupling networks usually employ at least two layers of decoupling to combat the nonideal characteristics of power-distribution networks. An ideal power supply has zero output impedance across all frequencies and load currents. However, the inductances associated with cables, bus bars, connectors, pc boards, and IC packages introduce impedances that increase with frequency. Thus, an IC's supply voltage is not rock-solid.

Bulk, or low-frequency, decoupling is the first layer of defense against unwanted impedances. This decoupling keeps the load voltage from drooping when there is a step change in current at the load that's too short for the power supply to respond. You need enough capacitance to supply all the charge required by the ICs during this time without letting the power-bus voltage droop below the limit allowed by your power noise budget, (Delta)V. The time scale for bulk decoupling is tens to hundreds of microseconds:

where T_PS is the power-supply response time and T_BUS is the power-bus response time.

You can see from this equation that the power-distribution response time depends on two components: the power supply and the interconnect, be it a cable or a bus bar. In this example, the interconnect dominates the overall response time. An inductance of 100 nH is a common number for 1 ft of cable. You need many 330-µF tantalum capacitors to keep low-frequency noise to 50 mV with this much inductance. Typically, designers use electrolytic cans at the power entry point and spread fewer tantalum capacitors across the board.

Using the value of (Delta)t; the worst-case step current, I; and voltage tolerance, (Delta)V, you can calculate the total necessary capacitance and total number of capacitors (NCAPS):

and

This large capacitance value points out two important facts. First, if your design requires a large amount of low- or mid-frequency current, place a local dc/dc converter near the loads. This local power source cuts the bus inductance and leaves only the pc-board and IC-package inductances. Second, you need a good feeling for your instantaneous current demand to make this method work.

The second layer of defense is the high-frequency decoupling capacitor array. These capacitors manage the effects of switching transients whose edge rates are 1 nsec or less. To be effective, a high-frequency capacitor has to have low parasitic inductance. This requirement means you must use small surface-mount components, such as multilayer ceramics, whose terminals are close, to minimize loop area.

You can use many approaches to estimate the number of high-frequency capacitors that a design requires. These approaches range all the way from rules of thumb from a TTL handbook to complex analyses of impedance vs frequency. The following equation is based on a simple principle: the high-frequency noise on a pc-board power plane comes from di/dt flowing though the effective inductance of the decoupling capacitors. You compute how much effective inductance your design can tolerate and still keep (Delta)V below your budget allowance. Then you use enough capacitors so that their parallel inductance is less than this value.

First, calculate

where NDRV is the number of drivers and DV is your budget allowance.

Then,

where 2 nH is the target number for the combined equivalent series inductance (ESL) of the capacitor and associated pc-board structures. Achieving an ESL of 2 nH requires careful attention to capacitor layout and routing. The pc-board vias and the trace from the surface-mount pad to the via contribute to the effective inductance of the capacitor. Vias should be as close as possible to the pads, and traces should be wide. The best placement of high-frequency decoupling capacitors for a bus distributes the capacitors across the solder-side surface of the board. The power planes themselves can contribute inductance, too, so proximity to the IC that requires the charge is an important factor.

Finally, keep in mind that these signal- and power-noise-budget examples are first-order approximations. A broad understanding of each noise component requires much more characterization work.

One rather significant question remains: whether all of these noise events add up at the same instant in time. This question is extremely difficult to answer. You must take some significant correlations into account. For example, it's not necessary to use an SSO noise figure that was obtained under fast-process, high-voltage, and low-temperature conditions. Fast process implies best-case timing, and the noise has a chance to settle out a bit before sample time. Quad Design Technology has taken a stab at solving this problem by coupling signal integrity and timing analysis. The company defines a "window of noise vulnerability," during which the noise margins have to be met. Signal excursions beyond the legal limits are allowable outside this window. However, a lot of difficult modeling is still necessary to refine this approach.

References

1. Prioste, Jerry E, "Exploit the potential of high-performance CMOS by selecting best interface," EDN, Oct 26 1995, pg 121
2. Hackenberg, John H, "Signal integrity in the VAX 8600 system," Digital Technical Journal, August 1985, pg 61.
3. Weast, Robert C, editor, Handbook of Physics and Chemistry, 52nd edition, The Chemical Rubber Company, Cleveland, OH, 1971.
4. Johnson, Howard H, and Martin Graham, High-speed digital design: A handbook of black magic, PTR Prentice Hall, Englewood Cliffs, NY, 1993.