Design Ideas: July 18, 1996

Using embedded-array programmable logic, it's possible to build multipliers that run faster than previous programmable-logic implementations. With the method shown here, you can make 4×4 multipliers that run at 73 MHz, as well as 8×8 multipliers that operate at 23 MHz. The design approach involves using embedded arrays as large look-up tables to store the possible results of a multiplication operation. The two multiplicands act as the address of the look-up table, which holds the correct product value at the appropriate address location. The embedded-array programmable-logic devices used in this example are Altera Flex 10K units.

The Flex 10K devices support multiplier design through the library of parameterized modules (LPM). The Flex 10K design software (Max+Plus II) automatically recognizes LPM multiplier symbols in designs and translates them into appropriately functioning look-up tables. You can configure an embedded-array block (EAB) in a Flex 10K device as an eight-input, eight-output look-up table, which means it can accommodate a single 4×4, 5×3, or 6×2 multiplier. Large multipliers (those with more than eight inputs) use two or more EABs.

Each EAB computes a single partial product, generated by a 4×4 multiplier. For example, the 8×8 parallel multiplier (Figure 1) uses four EABs (one for each partial product) to simultaneously generate four 4×4 partial products. Before adding the partial products, each partial product shifts to account for the 16n term. That is, each partial product shifts over n hexadecimal places, or 4×n bits. The adder assembles the final product by shifting the data into different bits. A two-stage adder normally effects addition, using 8 bits for the first stage and 12 bits for the second stage.

You can clock the parallel multiplier at 23 MHz. You can increase multiplier clock speeds by using registers to pipeline the design. Pipelining reduces the clock period but also introduces latency. You can use registers within the EAB for pipelining (Figure 2). An 8×8 multiplier uses three stages: a multiplier stage using four EABS and two adder stages with 8 bits for the first stage and 12 bits for the second stage. To pipeline the multiplier, each bit must go into a register after each stage. The design thus requires 21 registers for the first stage and 16 registers for the second stage. For the multiplier stage, each EAB has registers available at its inputs and outputs. For more information on building multipliers with embedded-array programmable logic, consult Altera's Application Note 53. (DI #1891)