Design Ideas: July 18, 1996

You can use variable-gain amplifiers (VGAs) in many types of systems, such as radio receivers, in which the input signal voltage depends on an uncontrolled variable, such as distance to the transmitter. In this type of system, you can use a VGA to ensure that the input signal amplitude matches the input voltage range of key components, such as ADCs and DACs, thereby maximizing the converters' dynamic range. The VGA in Figure 1 has high bandwidth, ranging from 115 MHz at high gain to 225 MHz at low gain, so you can use this circuit in the RF-signal path without degrading the signal. You can update the DAC in this circuit at 100 MHz, but the level-shifter op amp limits the speed at which you can update the gain of the VGA to 3 MHz. As configured, this VGA implements a calibration function with a 3-MHz DAC update rate.

The VGA design comprises a three-transistor, long-tailed pair configuration comprising Q₁, Q₂, and Q₃. By changing the base voltage of Q₃, the DAC (IC₁) varies the emitter currents of the long-tailed pair. Changing Q₃'s base voltage controls the gain according to the following equation, where K is a function of the emitter current and V_B3 is the base voltage of Q₃:

The gain-control and bias-stability parameters of the circuit depend on transistor matching, so the circuit uses an HFA3102-matched, long-tailed array for Q₁ through Q₃. The usable range of V_B3 is -0.8 to -4.4V, which corresponds to a gain range of 11.8 to -16.9 dB, respectively. This gain span is a total of 28.7 dB. The gain is proportional to R₄. Increasing R₄ increases the gain, but the gain span stays constant at approximately 28.7 dB. Increasing the gain causes a corresponding decrease in the frequency response.

R₂, R₃, and the -5V supply form a bias circuit that sets V_B3 to -0.8V when there is no DAC output current (the voltage across R₁ is zero), which occurs at a digital input of all ones. When the digital input is all zeros, the DAC output current is 20 mA, which develops 1V across R1. IC2 level-shifts and amplifies this voltage to yield V_B3=-4.4V. The CA5160 works well as the level shifter because its low bias currents do not affect the dc performance, and its bandwidth enables the gain to change at a rate as high as 4 MHz.

You should keep the input signal level at about 25 mV to prevent distortion. The signal path has an excellent frequency response because the HFA3102 is the only component in the signal path. A frequency-response plot for V_B3=-3V (gain of 10 dB) shows that the transfer function is well-behaved with no peaking and that the frequency response is 131 MHz at the -3-dB point. The DAC transfers the digital input to the internal registers on the rising edge of the clock pulses. This circuit uses the inverting DAC output to yield a positive increasing-transfer function, but you can obtain the inverse-transfer function by using the noninverting input (Table 1).

If fast updates are unnecessary, you can use a slower DAC than IC₁. However, you may also have to redesign the interface circuit (IC₂ and associated components) if the DAC-output-voltage swing changes. (DI #1895)