Design Ideas: July 18, 1996

The circuit in Figure 1a remembers the width of an input pulse at the in terminal. After the input pulse returns to zero, a trigger input causes an output pulse to occur at the out terminal. This output pulse is proportional to the width of the input pulse. R₂ and R₃ set this pulse-width ratio. For the values shown, the output pulse is half the width of the input pulse, but you can set the output-pulse width to any fraction or multiple by selecting the ratio of R₂/R₃. The circuit's operation depends on this resistor ratio but is independent of power-supply variation, temperature drift, and the tolerances of R₁ and C₁.

The waveforms in Figure 1b help explain the circuit's operation. The switches in S₁, a CD4066 quad-CMOS switch, are open if the input is at ground and closed if the input is at V_CC. Assume that C₁ has no charge for initial conditions; V_REF then determines the output of IC_1A. IC_1B, acting as a comparator, has a low output. Therefore, all CMOS switches are open. The input pulse closes S_1A, sinking a constant current from IC_1A's inverting input. This current causes a linear voltage rise at the output of IC_1A. When the input pulse ends, R₁ is open, and no further current flows. The capacitor maintains its charge, and the output of IC_1A is at a steady state.

A trigger input at this point closes S_1C, momentarily grounding the inverting input of IC_1B. The output of IC_1B goes high, closing S_1B and connecting R₁ to V_CC, which causes the voltage at the output of IC_1A to linearly decrease at a rate determined by the current through R₁. S_1C also closes, setting the voltage at IC_1B's inverting input to V_MIN, approximately 0.5V. When IC_1A's output voltage drops below V_MIN, IC_1B's output goes low, and all switches are again open, and the net voltage across C₁ is zero.

Using the values of R₂ and R₁ to select V_REF, you can make the output pulse any multiple or fraction of the input pulse. This feature is handy for generating sonar-echo replies or other applications in which a delayed pulse whose width depends on the input pulse must be returned. Choose R₁ and C₁ so that the output of IC_1A does not saturate at the longest pulse anticipated. For the circuit in Figure 1, this number is approximately 2.7ŚR₁C₁. (DI#1896)