Design Ideas: July 18, 1996

Figure 1 shows a common way of implementing an I/O decoder for the ISA (or similar) bus. Under control of the decoder chip, a 74LS245 buffer separates the onboard data bus from the ISA bus. If the DIR and G/ signals derive only from decoder inputs, they change state simultaneously at the beginning and end of an I/O cycle. Such behavior can cause undefined operation of the buffer with possible contention on the local or ISA bus (particularly if you use a faster version of the 245).

You can solve this problem by using more complex equations for DIR and G/:

!DIR = (!IOR/ & !AEN & (Address == xxx)) # (!DIR & !G/); !G/ = (!IOR/ & !AEN & (Address == xxx)) & !DIR) # (!IOW/ & !AEN & (Address == xxx));

This solution does not require additional macrocells and assures DIR stability before G/ goes active and after it becomes inactive (Figure 2). The assertion of G/ during read cycles delays until DIR becomes stable. The equation for DIR is equivalent to an R-S latch that is set by active IOR/ and cleared by inactive G/. For correct operation of this latch, the IOR/ and IOW/ pulses must not overlap. This situation is always true for real-bus operation but requires the addition of one idle state between reads and writes in the test vectors for PLD testing. (DI #1898)