Editorial: August 1, 1996

Ten years of EDA- and ASIC-company visits and attending the Design Automation Conference (DAC) had nearly convinced me that ASIC vendors would never be ready to meet the needs of system designers. ASIC vendors seemed quite content to target the much smaller group of IC designers, their traditional target audience. This year's DAC was different for me, however. Three meetings in particular left me with the impression that the tide has changed for the better.

At a breakfast meeting in the Las Vegas Hilton, Altera's vice president of marketing, Erik Cleage, introduced the company's $7995 MegaCore function library. Initially, the library contains the following cores: an 8237 DMA controller, an 8255 parallel I/O module, an 8259 interrupt controller, a 6502 µP, a 6402 UART, a 16450 UART, an 8251 UART, and a 6850 ACIA (asynchronous-communications-interface adapter). Each function in the library consists of an optimized, postsynthesis netlist file in Altera's hardware-description language, along with simulatable Verilog- and VHDL-design files. Altera plans to add more modules in 1996, including a PCI initiator/target module, FIFO memories, other µP peripherals, and DSP functions.

Altera's announcement places even more pressure on ASIC vendors to offer similar large-scale macro blocks. System designers have long designed with such blocks, usually buying them in 40-pin DIPs. In the ASIC world you don't buy chips, however, you buy "intellectual property"—a poorly selected name if there ever was one and yet another indication that ASIC vendors do not truly understand system designers. If lawyers designed electronic systems, they might enjoy the idea of incorporating "intellectual property" into their designs. I have my doubts as to how appealing this name is to engineers.

The second discussion that led me to believe that ASIC vendors were almost ready for system designers was with Dieter Metzger, president of Compass Design Automation. Compass offers design tools and physical cell libraries that work across several different ASIC-fabrication processes. They even work over a range of lithographic geometries, as long as you're willing to accept different speed ranges from your design. Just as you are not confined to one vendor's chips when designing at the board level, Compass' products allow you to be relatively independent of the ASIC vendor at the chip level. That's a freedom system designers demand.

Finally, I had a chance meeting with my friend Bernie Rosenthal, who is director of marketing at Silicon Architects. Bernie challenged me by asking how anyone would be able to make use of the approximately 100 million transistors that will be in soon-to-be-built deep-submicron ASICs. I suggested taking eight Pentium µPs (3 million transistors each) and using Corollary's C-bus II multiprocessor bus to link the eight processors. With 2 Mbytes of write-back cache per processor on chip, you're at about 100 million transistors, and you've got one hell of a multiprocessor for a high-end server.

As you can see, a system designer has little trouble specifying large ASICs if the appropriate macro blocks, or "intellectual properties," are available. It took me just the preceding paragraph to create a complete, top-level description of a 100 million-transistor ASIC that someone else could easily understand. As ASIC vendors continue to ride their newly rediscovered "system-on-a-chip" bandwagon (the phrase has actually been used to refer to µCs for at least 20 years), they will continue to rub shoulders with systems designers who don't design µPs or UARTs one gate at a time. After my conversations at this year's DAC, I now have no doubt that the ASIC vendors are getting the message.

Steven H. Leibson
Editor in Chief