Design Ideas: August 1, 1996

The circuit inFigure 1 generates a 4- to 5-kHz output frequency that precisely sweeps a variable amount of 1 to 100 Hz over a variable time of 0.5 to 5.0 sec (1000-to-1 rate range). The resolution is 1 Hz, and worst-case accuracy during the sweep is 3 Hz (0.06%). This circuit was designed to run from an 8-bit PC ISA bus, but any µC with an 8-bit bus and the appropriate control signals can control the circuit. With a 25-MHz clock source, this circuit can generate a frequency as low as 3.052 kHz, and the theoretical maximum is 12.5 MHz, although frequency sweeping would start after approximately 1.3 msec.

The circuit contains three counters: the DT counter (IC₁), the up-down counter (IC₄ to IC₆), and the fast counter (IC₇). Exclusive-OR gates IC_2A and IC_2B allow you to use two clocking signals for normal operation and for data preloading. IC_3A's data latch determines the frequency-sweep direction. IC₉ holds the lower byte of data for loading the 16-bit counter, IC₁. (You can omit this counter if you use a 16-bit bus.) IC_2C works as an inverter to generate the WE signal to IC₁ for data loading. The circuit clocks the fast counter at 25 MHz to provide the 1-Hz resolution of the circuit at the 4- to 5-kHz operating frequency.

Figure 2 shows the related timing diagram. A sequence of control signals resets and preloads the timers. You can generate the control signals to generate the desired clock and latch signals for this initialization using a PLD, logic gates, or direct control from a data port of a µC. The sequence is as follows:

• A data write generates a logic low to reset the circuit (INIT).
• A data write to the low byte of the DT counter generates a falling edge (LATCH_DT).
• A data write to the high byte of DT counter generates a logic high (LD_DT) and a rising edge (CLK_DT).
• A data write to the high byte of the up-down counter generates a logic low (LOAD_U/D_HI) and a falling edge (CLK_U/D).
• A data write to the low byte of up-down counter generates a logic low (LOAD_U/D_LO) and a falling edge (CLK_U/D).
• A data write generates a rising edge to start the circuit (START/STOP).
• A data write generates a rising edge to stop the circuit (START/STOP).

After initialization, the up-down counter holds a value of half the starting output frequency, at 40 nsec/bit. The value in the DT counter, which is based on the sweep rate and output frequency, determines the update rate of the up-down counter.

Once started, the fast counter starts counting from zero. (The first output is garbage.) When IC₇ overflows (Q-output high), the first real data loads into the fast counter from the output of the up-down counter, through IC_8A using the XTR input. That same load signal clocks the DT counter, which increments its value from the preloaded value toward overflow. When the DT counter finally overflows, the circuit issues a clock to the up-down counter, through IC_3B (for synchronization with the 25-MHz clock) and IC_2B.

The up-down counter then changes its value up or down depending on the initialization of IC_3A, causing a fine step change in the next half-period of the output frequency. The actual frequency output comes from the Q/2 output of IC₇ because each overflow of the fast counter is half the output period. For no frequency sweep, simply initialize the DT counter with 0, so that it will not overflow for more than 6 sec at a 5-kHz output. The controlling hardware must control the generated pulse width via the START/STOP control.

Because the fast counter operates from a fixed 25-MHz clock, the frequency change forced by a changing up-down counter value is slightly nonlinear. For example, because 1/4900 Hz×1/5000Hz=4081 nsec, changing the counter value 100×40 nsec produces some final error, as well as a slightly nonlinear change from 5000 to 4900 Hz. The best method for calculating the counter value is as follows:

• Calculate the starting and ending up-down counter value from the desired output frequencies:

• Calculate the DT counter value based on the up-down counter values, the output pulse width, (PW), and the frequency sweep amount (FSWP), where |(x)| means absolute value:

(DI #1897)