Design Ideas: August 1, 1996

The design of a shared-memory interface for the ISA bus commonly requires a relatively complex arbiter, which grants access to an onboard device or to the ISA bus. If an on-board device requires only infrequent accesses, the circuit in Figure 1 can eliminate the need for the arbiter. Local access occurs during the execution of an ISA refresh cycle, thereby eliminating any risk of contention. The RFRSH line signals the beginning of the refresh cycle; as long as this signal is active, the local device has full control of the memory. As Figure 1 shows, you must disable the ISA-address decoding during a refresh cycle.

The width of a RFRSH pulse is approximately 400 nsec (3.5 to four ISA clocks), and the cycle repeats every 15 µsec. Because the ISA bus generates these cycles with some irregularity, the local device should be prepared to wait as long as 25 to 30 µsec for an access. The local access should always be completed before the end of an RFRSH pulse. The system timer 1 sets the frequency of ISA refresh cycles, and you can modify the frequency with software.

A circuit based on the concept described here served to interface VRAM in a frame-grabber board. An onboard controller uses the nearest RFRSH signal following the end of each scan line (occurring every 64 µsec) to perform a video-transfer cycle (specific to VRAM). (DI #1902)