Out in Front: August 1, 1996

Two new PLDs from Philips, the 3V PZ3032 and the 5V PZ5032, have 32 macrocells each. The 3V version has an 8-nsec delay from any input to any output and a standby current of less than 100 µA. The system measures worst-case dynamic power by implementing 16-bit counters operating at 50 MHz. Worst-case dynamic power is 20 mA. The device achieves its high performance and low power by replacing ordinary constant-current-drain sense amps with a chain of CMOS gates.

The architecture provides five dedicated product terms for each macrocell, but you add as many as 32 more product terms, thus adding a 2.5-nsec delay. The architecture, which the company calls the "eXtended programmable-logic array" (XPLA), doesn't steal product terms from adjacent macrocells but uses PAL and PLA arrays to bring extra product terms to every macrocell that needs them. Multiple outputs can share the additional product terms.

The 5V PZ5032 offers a 6-nsec pin-to-pin delay. The 5V device also offers less than 100-µA standby current. Worst-case dynamic power for this device with 16-bit counters operating at 50 MHz is 30 mA. The 5V device's architecture is identical to that of the 3V device. Using more than five product terms, for a total of as many as 37, results in a 2-nsec additional delay.

The PZ3032-8 costs $11.50 (10,000), and the PZ5032-7 costs $7.50 (10,000) in 44-pin PLCC packages. The company offers a PC/Windows-based development tool ($95), or you can use design tools from Synario Design Automation (Redmond, WA) and MINC (Colorado Springs, CO).

—by Doug Conner

Philips Semiconductor, Sunnyvale, CA. (800) 234-7381, http://www.semiconductors.philips.com/ps/.