Electronic Design Automation: August 1, 1996

Design software sculpts MACH-5 logic devices.

With the MACHXL 5.0 tool suite, you can design, synthesize, place and route, simulate, and perform timing analysis on designs based on AMD's MACH-5 family of programmable-logic devices. In addition to the high-density MACH-5 parts, the software also supports AMD's MACH221, MACH-231SP, and MACH-211SP devices. Release 5.0 includes a simulation waveform viewer and optional Viewlogic and OrCAD schematic interfaces, as well as timing- model outputs for Verilog or VHDL simulators. MACHXL 5.0 runs on PCs under Windows 3.1, 95, and NT. Introductory prices start at $995. Minc Inc, Colorado Springs, CO. (719) 590-1155.

Tool set offers CPLD/FPGA design capabilities.

After acquiring IST of Grenoble, France, the vendor is integrating its PLDesigner-XL PLD- and CPLD-design program with IST's ASYL+ FPGA/ASIC-synthesis tool suite. Called PL-Link, the software combination gives you CPLD and FPGA partitioning, synthesis, optimization, mapping, and fitting technologies in a single tool suite. PL-Link supports devices from Actel, Altera, AMD, Crosspoint, Cypress, Lattice, Lucent Technologies, Philips, Quicklogic, and Xilinx. Offered on PC/Windows platforms, PL-Link costs $9995. Minc Inc, Colorado Springs, CO. (719) 590-1155.

Connector models join signal-integrity software.

Starting with the LineSim for Windows preroute analysis tool, the vendor will include models of Amp Inc's electrical connectors with the vendor's signal-integrity and -analysis software. The model library, created by Amp, encompasses >60 connector types. Each model includes a detailed electrical characterization of a portion of a connector. You can load the model into LineSim by clicking on a transmission-line symbol and then choosing the appropriate model from a customized dialogue box. LineSim costs $1495, with no additional charge for the connector library. Hyper-Lynx Inc, Redmond, WA. (206) 869-2320.

Upgraded EDA tool adds distributed fault simulation.

Enhancements to the Silos III Verilog HDL-based logic- and fault-simulation system adds an active-HDL code-coverage tool for identifying HDL code that is inactive during simulation. Version 96.100 also offers a single-kernel simulation engine with distribution capabilities. Distributed fault simulation incurs a minimum of overhead to partition the fault list to the available CPUs on a given network. With an improved Programming Language Interface (PLI), Silos III lets you use the same executable for each combination of user-written PLI code. Silos III runs under Unix and Windows, and prices start at $3000. SimuCAD Inc, Union City, CA. (510) 487-9700.

Program generates testbenches, verifies output.

Testbencher Pro, an en-hanced version of the WaveFormer timing-diagram editor, verifies simulation output by detecting glitches, bad-logic levels, and violations of setup-and-hold times. Testbencher generates Verilog and VHDL testbenches with extra code that verifies that the system meets graphically specified conditions. The software's built-in scripting language lets you customize testbench output. Testbencher Pro costs $1500 on all Windows platforms. SynaptiCAD, Blacksburg, VA. (800) 804-7073.

System emulators in-crease capacity, speed.

The System Explorer MP4 and MP4 Pro system emulators verify designs and hardware/software integration in real time before hardware fabrication. Both systems contain a board with four field-programmable interconnect components for a total of 2880 free holes and 448 I/Os to support as many as 20 FPGAs. This increased capacity over previous System Explorer products lets you emulate systems with as many as several hundred thousand gates. Eight low-skew clocks avoid timing delays and allow emulations to run as fast as 50 MHz. Prices start at $85,000. Aptix Corp, San Jose, CA. (408) 428-6200.

Device libraries sharpen FPGA/CPLD design tools.

The latest versions of OrCAD Simulate and Or-CAD Capture add comprehensive schematic libraries, VHDL-simulation models, and direct netlist interfaces to device vendor back-end tools to streamline FPGA and CPLD design. V6.1 of Simulate includes VHDL simulation models, and V7.0 of Capture supplies logic macros and primitives, both for devices from silicon vendors, including Actel, Altera, AMD (through Minc), Lattice, and Xilinx. You can purchase the Windows-based programs as a bundle for $3995. OrCAD, Beaverton, OR. (503) 671-9500.

Software combines VHDL design entry and synthesis.

Active-Synthesis provides turnkey VHDL design entry for complex PLDs and FPGAs, supporting VHDL entry, state-machine diagrams, and VHDL synthesis. The Windows-based software comes with hardware-description-language design wizards that automatically generate the skeleton de-sign, synthesis templates, and VHDL references. Ac-tive-Synthesis works with the Active-HDL Editor, which provides automatic VHDL syntax checking and source-code error navigation. The program runs on PC platforms and supports Xilinx devices. Prices start at $2995. Aldec Inc, Henderson, NV. (702) 456-1222.

Preroute analysis program checks signal integrity.

LineSim for Windows is an interactive analysis tool that lets you investigate signal-integrity issues early in the design cycle, before pc-board layout. By entering hypothetical interconnection scenarios, you can perform detailed signal-integrity analyses to predict effects such as overshoot and undershoot, long settling times, and glitching. ICs are modeled in two formats: Ibis or HyperLynx's data-book method. LineSim costs $1495. HyperLynx Inc, Redmond, WA. (206) 869-2320.

Design environment performs interactive synthesis.

The Leonardo logic-synthesis design environment lets you interactively control synthesis, selectively optimizing different parts of your design for speed or area. Using Leonardo, you can also change the design hierarchy to fine-tune portions of the design that require different constraints. Leonardo runs on Sun and HP700 Unix platforms, as well as Windows 95 and NT. The device is available in the third quarter. Exemplar Logic Inc, Alameda, CA. (510) 337-3700.

Tools help build embedded-array and standard-cell libraries.

The InConcert physical library-de- velopment environment comes with reference libraries for the vendor's embedded array (HDEA) or standard cells (HDC), as well as AMAP, software that maps libraries from 0.8 µm to 0.35 µm or below. InConcert offers 20 to 40% die-size improvement over existing cell architectures, as much as a 15% gain in performance, and as much as 50% power savings at the chip level. The development environment supports >30 EDA-software and -hardware tools. Prices start at $500,000. Aspec Technology, Sunnyvale, CA. (408) 774-2199.

Software tweaks pc-board manufacturing processes.

EDAassimilator manufacturing-synthesis software lets you analyze designs and manufacturing processes early in the design cycle to provide manufacturability, cost, yield, and assembly analyses. The software helps to identify assembly-process inefficiencies or design weaknesses before you build prototypes. The EDAassimilator tool suite consists of several discrete tools that you can apply selectively and in any order to optimize current and proposed production systems. Prices for the software, which is offered on Unix and Windows platforms, start at $10,000. Harris EDA Inc, Fishers, NY. (716) 924-9303.

Processor and filter functions work with logic family.

The first functions developed under the Altera Megafunction Partners Program (AMPP) are a V6502 microprocessor from V Automation and a 32-tap FIR filter from Integrated Silicon Systems. Both the V6502 and filter target the FLEX 10K logic device family. The V6502 uses 32% of the EPF10K50 device, leaving nearly 35,000 gates free to implement other system functions. The 12-bit parallel FIR filter, which processes data at 171 kHz, requires 20% of the logic elements in the EPF10K50 and uses seven embedded-array blocks. An encrypted textual description of the V6502 costs $2500 for a one-year node-locked license. The filter costs $9500 for a one-year node-locked license. Altera Corp, San Jose, CA. (408) 894-7000.

Hierarchical layout tool permits subcircuit reuse.

The Visula pc-board-layout tool set enables subcircuit reuse and concurrent board layout and is an option for the Visula layout editor. The Visula design-partitioning software uses a hierarchical approach to layout, allowing more than one designer to work in parallel on the same design. You can also reuse areas (complete designs or selected parts) of circuitry that have already been placed, checked, and tested. The tool set performs thermal, EMC, and high-speed analyses on each design partition. Visula design-partitioning costs about $15,000 per license and is offered on Sun, Hewlett-Packard, NEC, and DEC Alpha workstations. Zuken-Redac, Santa Clara, CA. (408) 562-0177.

Software analyzes power and ground planes.

A software program for modeling transient behavior in ground and power planes lets you analyze the effects of various power- and ground-plane-layer alternatives, as well as component-decoupling strategies and power/ground-plane noise voltages. AC/Grade analyzes the distributed effects on ground planes, helping you determine which approach best suits your application. AC/Grade runs under Unix and works with the XTK signal-integrity program. The stand-alone tool costs $25,000. Quad Design, Camarillo, CA. (805) 988-8250.

Analysis software models BGAs and PGAs.

Enhancements to OptEM Package, a package modeling and analysis tool, let you model ball-grid arrays (BGAs), pin-grid arrays (PGAs), and bonding wires. The program models package traces from DXF, Gerber, or GDS-II layout data. It then generates interconnect Spice models and subsystem models for use with the vendor's Interconnect Designer, a signal-integrity and parametric-analysis program. OptEM Package also lets you identify where the power- and ground-return paths are in each connection model. The software runs on Hewlett-Packard and Sun SPARC workstations. Prices start at $35,000. OptEM Engineering Inc, Santa Clara, CA. (408) 248-9165.

Software programs diverse devices.

V4.7 of CUPL development software for PLD and FPGA design now supports Atmel ATF1500 and ATF1500QFP; Cypress C381A, C382A, C383A, C384A, C385A, C386A, and C387A; QuickLogic QL8x12B, QL12x-16B, QL16x24B, and QL24x32B; and Xilinx XC400E and XC5200 devices. CUPL 4.7 also includes a utility program that takes an existing Open PLA-formatted file and derives a CUPL-source PLD file. The programming software costs $2495. Logical Devices Inc, Golden, CO. (303) 279-6868.

Power-analysis tool enhances IC-design planning.

Release 2.1 of Watt Watcher, a program that estimates IC-power dissipation early in the design cycle, provides an interactive environment to help you find and fix power issues before they become a problem. The updated software includes cross-probing between power-analysis re-sults and Verilog-HDL statements. New delta-propagation techniques allow Watt Watcher to monitor the effects of small changes in activity on circuit performance and to analyze circuits for sensitivity to various input activities. Watt Watcher runs under SunOS, Solaris, and HP-UX and costs <$60,000. Sente Inc, Chelmsford, MA. (508) 244-1100.

Initiative results in value-based physical-design solution.

Part of the Fabless Semiconductor Initiative (FSI), the Epoch/FSI physical-design suite combines enhanced Epoch libraries, generators, and design tools with bundled support services and flexible business terms. The physical-design alternative costs 40 to 50% less than comparable library and point-tool solutions. Each seat of Epoch/FSI includes training, help with the first design, and design-rule updates for one year. Rental programs, lease-to-buy options, and royalty agreements are also available. Epoch/FSI runs on Hewlett-Packard and Sun workstations, with prices starting at $248,000. Cascade Design Automation, Bellevue, WA. (206) 643-0200.

Megafunction library offers risk-free evaluation.

The MegaCore function library is a collection of industry-standard megafunctions for the vendor's PLDs. The first entries include an 8237 DMA controller, a 6502 8-bit processor, a 6402 UART, a 16450 UART, an 8251 UART, a 6850 asynchronous-communications-interface adapter, an 8259 interrupt controller, and an 8255 parallel I/O controller. Using the company's OpenCore technology, you can evaluate MegaCore functions before you purchase them to see how the function fits into one of the company's devices. If you want to program a device, you can then purchase the MegaCore library for $7995. Altera Corp, San Jose, CA. (408) 894-7000.