Design Feature: August 15, 1996

It's difficult for data-acquisition systems—especially those designed to operate in a PC slot—to actually yield the best possible performance. For example, a number of error sources, such as analog- and digital-system errors or RF contamination from external sources, can corrupt precise measurement. As a result, the actual accuracy of many off-the-shelf 16-bit data-acquisition boards is at best in the 13- or 14-bit range.

If your application acquires microvolt signals, a viable data-acquisition system must offer superior low-noise, filtering, and decoupling design, as well as good analog layout. You can achieve this goal by pinpointing specific error sources in each functional stage from the front end to the µP interface. In addition, you can use accuracy-enhancing techniques for further improvement. Some of these techniques are as simple as proper bypassing, but, sometimes, the standard 0.1-µF guideline is inappropriate.

Figure 1 shows an overview block diagram of the complete data-acquisition system. (Note: The relevant schematics are Figure 2, the system front end; Figure 4, the A/D converter; and Figure 6, the power supply.) Each functional block is subject to a variety of error sources, including dc errors resulting from the inherent offset voltage and current of each IC or from finite, frequency-dependent CMR. You also need to minimize performance degradation due to power-supply noise, which is important if a switching supply or dc/dc converter is part of the design.

The example in Figure 1 takes into consideration analog filtering in front of the multiplexer and the A/D converter, shielding and active guard drive, implementation of galvanic isolation, and differentiation in the routing of ground traces. By comparing your preliminary error-budget analysis (based on the individual specifications of each IC data sheet) to the desired system precision, you can select the necessary accuracy-enhancing techniques.

Input signals are bandwidth-limited by the passive low-pass filter in front of multiplexer IC₁. Its output signal connects to the differential inputs of the digitally programmable instrumentation amplifier, IC₂, a pin-grid array (PGA) that amplifies the signal to match it to the full-scale input range of the ADC. The signal then passes through another lowpass filter; in this case, it is an active, fast-settling, third-order Sallen-Key filter using op amp IC₈.

The 16-bit ADC, IC₇, has a serial digital-data interface, which simplifies the galvanic isolation of the ADC interface to the FPGA, implemented by two data couplers, IC₅ and IC₆. The FPGA is the control center of the data-acquisition system and receives its initial configuration every time the power cycles from a PROM. Through the FPGA, the user controls the selection of the input channel of the multiplexer and the gain range of the PGA. More interesting, you can use the FPGA for averaging and chopper techniques, both of which are instrumental in achieving 20-bit performance. A dc/dc converter provides the ±15V supply that many of the analog ICs require, although the rest of the circuitry runs from a 5V PC supply.

In general, a differential configuration for inputs (in this case, four inputs, selected via the multiplexer) is better than a single-ended configuration because common-mode signals appear only in reference to the noncritical signal ground. Any current flowing between the signal source and the acquisition card flows in this signal ground, which, in turn, prevents interference between the input channels. For example, resistors R₁, R₂, R₁₁, and R₁₂ together with capacitors C₇, C₈, and C₁₂ constitute the passive lowpass filter for channel 0 (Figure 2). (The discussion of this filter applies to the other three channels as well.) The filter is located in front of the multiplexer and attenuates high-frequency components that may be superimposed on the input signal along with unwanted common-mode signals.

A by-product of this input filtering is that radiated noise that may be received as a result of long signal lines cannot be seen directly at the input of the first IC. This noise can cause additional error voltages because of the rectification effect of a p-n junction. Both R₁ and R₂ share capacitor C₁₂ from the lowpass filter in each of the two differential-input lines. The -3-dB roll-off frequency is 252 Hz, determined by the equation:

You can estimate the required -3-dB frequency of a single-pole lowpass filter or a given resolution and signal frequency using the equation:

For example, for a 16-bit resolution and a 1-Hz signal bandwidth, the lowpass filter should roll off at 256 Hz, using the component values of this design. Adding capacitors C₇ and C₈ to the lowpass filter creates a symmetrical filter for ac common-mode noise. With R₁=R₂=309(ohm) and C₇=C₈=47 nF, the corner frequency is 10.9 kHz. This filter becomes very important if you want to handle millivolt-range input signals and maintain high resolution and accuracy.

For dc and low-frequency signals, the CMR of the programmed instrumentation amplifier, IC₂, is typically 100 dB at a gain of 1V/V. The CMR increases to approximately 123 dB at the highest gain of 1000V/V. However, the CMR is frequency-dependent, decreasing with increasing common-mode frequency, typically with a roll-off of a first-order network and with a slope of -20 dB per decade. You should limit the common-mode S/N bandwidth to low frequencies to preserve high accuracy. You can use the lowpass filter shown; its single-pole response and attenuation rise of 20-dB per decade matches the loss of the PGA's CMR.

Using the values from Figure 2, the total CMR does not drop below 75 dB. You can get higher rejection by reducing the -3-dB frequency of the filter. However, the component change is limited to capacitors C₇ and C₈. If you modify resistors R₁ and R₂ to increase rejection, this alters the corner frequency of the signal lowpass filter. Watch the tolerances of the selected components in this lowpass-filter design; although the absolute tolerance of each component is not important, the relative matching between component pairs is.

For example, the time constant of R₁/C₇ should equal the time constant of R₂/C₈. In reality, this is not practical and, therefore, a remaining mismatch is always present. This situation also results in a mismatch of the corner frequencies of the common-mode filter, which means that the voltage across capacitor C₇ is different from the voltage across C₈, causing an imperfection in the suppression of any common-mode signal. The CMR dips at a frequency close to the -3-dB point of the common-mode filter, 10.9 kHz in this case. Fortunately, the dip of the CMR curve depends on the size of capacitor C₁₂ located across the two capacitors, C₇ and C₈, because C₁₂ shunts the common-mode signal between the differential-input lines, thus acting as a time-constant balancing capacitor. As a rule of thumb, the value of capacitor C₁₂ should be 20 to 50 times larger than that of capacitors C₇ and C₈.

Because a differential input has no connection to ground, an open differential input floats and eventually hits the supply rail. By using termination resistors R₁₁ and R₁₂ from each signal line to ground to ensure a defined potential for the inputs, the bias current from the PGA flows through those resistors to ground. To keep the voltage drop due to the ±0.5-nA bias current below 500 µV, these resistor values should be less than 1 M(ohm). At the same time, the two biasing resistors define the input impedance for each channel. Depending on the nature of the signal source, such as bridge-type sensors, you can remove those resistors.

Gain stage is critical

The full-scale input range of the data-acquisition card is ±10V, and the signal amplitude should match the input full-scale range of the subsequent ADC to achieve the best S/N ratio. Two control lines set gain to one of four values. Depending on the application, you can choose PGAs with gain factors of 1, 2, 4, and 8 or 1, 10, 100, and 1000. Do not use the PGA's offset trim to adjust for total system offset. You can null the offset that is not produced by the PGA to increase the temperature drift by approximately 3.3 µV/°C per 1 mV of offset adjustment.

The PGA used makes it possible to access the outputs of the input amplifiers. The data-acquisition system uses this amplifier for another accuracy-enhancing technique: the active guard drive. By using resistors R₄₄ and R₄₅, connected to IC pins VO₁ and VO₂, you can generate the mean common-mode voltage of the input. You can combine the two resistors at the noninverting input of buffer op amp IC₁₂. The op amp then drives the "guard" voltage that is connected to several pins of the input connector. Because the op amp does not drive a resistive load, it is only a (parasitic) capacitive load. You can decouple its output through the 220(ohm) resistor, R₄₃.

During the layout phase, you should place several guard traces (driven by buffer IC₁₂) around the inputs and their components, such as the resistors and capacitors of the passive-input lowpass filter and the signal lines up to the PGA. Those traces create only small parasitic capacitors to their adjacent traces and, in first-order approximation, no current flow occurs. The advantage of using active guard drive is that the shielding of the outer conductor of the chosen cable is, in most cases, connected to analog ground and, therefore, has a 0V potential. In reality, there are lumped parasitic capacitors between the "hot" signal line and the shielding, and their value depends on the potential between them. This situation means that error signals can be capacitively coupled into the signal. Using an active guard eliminates this problem completely, because the potential between the shield and the signal line is driven to 0V, which in turn cancels all parasitic capacitors.

To control the noise bandwidth at the input of the ADC and attentuate any unwanted frequencies that may cause interference with the signal, you should use a lowpass filter between the output of the PGA and the input of the converter. This filter significantly improves the S/N ratio, especially when operating the PGA at a gain of 100 or 1000. The active component of the filter is the low-noise dual op amp, IC₈, which has a better settling time than standard passive RC-filters. You determine the -3-dB corner frequency of the filter by

which is set to 23.4 kHz. Diodes D₁ and D₂ cause the filter to respond five to six times faster to input pulses than a normal filter would respond. Figure 3 shows the pulse response of the fast-settling filter, with a settling time of approximately 13 µsec, compared to 74 µsec for the passive RC filter. To optimize your system for a high throughput rate, it is important to keep the settling times as low as possible. Note that you do not simply add settling times together to calculate the overall settling time; instead, use the square root of the sum of their squares. You can further improve the roll-off behavior of the active filter using R₄₆ and C₆₄, a single-pole RC-filter in the input of the op amp. The second op amp within IC₈ buffers the output of the active filter from the input of the ADC to ensure that the conveter is driven by a "solid" low-impedance source.

To realize full resolution of the low power, 16-bit sampling AC, you must make sure that any error voltage does not exceed 0.5 LSB=153 µV. Physical separation of the error-producing digital circuitry from the sensitive analog portion is the most successful way to minimize performance loss. Two digital data couplers, IC₅ and IC₆, provide galvanic isolation between the analog and digital grounds. The data couplers act as transceivers, and their 50-Mbaud data rate is fast enough to establish the galvanically coupled logic interface to the ADC (Figure 4).

The frequencies on the serial-data and -clock lines are approximately 1 MHz. Even though this is not a high speed, you can get line reflections and subsequent undershoot and overshoot (ground bouncing), which may introduce dynamic errors to the system. To prevent this scenario, place a 100(ohm) resistor in series with each of the four interface lines between the data couplers and the ADC.

Many ADCs have separate pins for their analog and digital ground connections because the lead frame and wire bond have a large parasitic inductance, and current spikes on the digital side cause signal bounce on the analog side. To connect the two ground pins properly to the rest of the system, you should treat the ADC as an analog IC and provide solid and quiet ground by providing either a ground plane where the analog and digital grounds connect or using wide and short traces for each of the grounds and return them to a single common point.

To accommodate a variety of sensors, such as bridges, you can select the excitation voltage of 2.5 or 5V using jumper J₄. To achieve minimum drift and, thus, maximum accuracy, the internal reference voltage of the ADC provides stable 2.5V voltage. The advantage of this, compared to using another separate reference IC, is that this configuration tracks the drift of the ADC. Precision-difference amplifier IC₂₀ implements a 2V/V gain block, followed by open-loop buffer IC₁₃, which provides the current drive of this sensor-excitation circuit. By this design, the precision amplifier is not subject to power dissipation, which causes additional heating of the chip and, thus, drift. The positive supply of IC₁₃ (pin 7) connects to 10V instead of the normal 15V. You do this connection to reduce the power dissipation in the buffer and to separate the flowing sensor current from the rest of the analog circuit.

This circuit supports both a high-resolution 20-bit mode and a faster 16-bit mode. The faster conversion is helpful when you are following a signal's settling time or in cases when the input signal has a higher rate of change. After the signal has settled within a certain error band, you direct the acquisition circuit to switch to high-resolution mode. Regardless of the selected mode, it is critical that you allow the system enough time to settle to the required level of accuracy.

The FPGA implements averaging, another accuracy-enhancing technique (see box, "Resolution enhancement pays off"). If you take a capable ADC and oversample the signal frequency (above the Nyquist rate), then adding n samples together and dividing the resultant sum by n produces the average value of those samples. This approach enhances resolution and also reduces the bit rate to the PC. (Note that the integral linearity of the system depends only on the ADC itself and cannot be reduced by this averaging process.)

1	F	F	F	E	0	0 	
1 	1111 	1111 	1111 	1110 	0000 	0000

F	F	F	F	0 	
1111 	1111 	1111 	1111 	0000

Another advantage of the oversampling and averaging technique is that you can use a much simpler antialiasing filter with a less demanding roll-off slope, because the sampling frequency is much higher than the maximum input frequency. By skillfully selecting the sampling frequency, the circuit can reject error frequencies, such as 50- or 60-Hz line noise, due to the sine x/x frequency response typical for each time-discrete-sampling process.

Chopper further reduces error

The acquisition of small input signals requires you to use a high gain in the input amplifier. Unfortunately, errors, such as offset voltage, offset drift, and low-frequency (1/f) noise amplify at the same time, which significantly limits the achievable reproducibility and resolution. To reduce these sources of error, you equip the gate array with a chopper function (Figure 5).

The timing of the chopper is set so that it changes states four times during one chopper period. When activating the chopper function, two of the four differential inputs of the multiplexer combine into one measurement channel. Through external connections, the positive input of channel 1 is shorted to the negative input of channel 2 and vice versa.

For example, you can apply an input voltage to be measured to channel 1. This application means that the same signal voltage lies across the input pins of channel 2 but with reversed polarity. Now, in the first quarter of one chopper period, the signal is read in via channel 1. During the second quarter, the signal appears at the multiplexer via channel 2 but with inverse polarity. For the third quarter, the multiplexer switches back to channel 1, and the final quarter is read in again via channel 2. This process continues; the input voltage contributes to the output by summation in both switch positions. The total noise includes all error signals superimposed onto the test voltage during the signal conditioning and the A/D conversion.

However, when the switch is in the upper position, you add the error voltage to the output. With the switch in the lower position, you subtract the error voltage from the result. Hence, this chopper process eliminates all error voltages that remain constant during one chopper period, such as offset voltages and drifts. In addition, the chopper function attenuates the 1/f noise, particularly the noise from the input amplifier, which is in the frequency range of 0.1 to 60 Hz. Without the chopper, any noise signals fall into the same bandwidth range as the signal itself (solid line). Although the signal response remains the same, the chopper significantly attenuates the 1/f-noise (dashed line).

Two miniature dc/dc converters step up the supply voltage from 5V into the ±15V and 10V needed by the analog circuitry (Figure 6). The inductive coupling of the dc/dc converters also establishes a galvanic isolation between the primary and secondary side to preserve the strict separation between analog and digital supplies. These converters typically switch at approximately 500 kHz, and their tiny packages incorporate only limited reduction of the switching noise.

It's important for designers to understand specifications for these converters. For example, manufacturers may specify the output noise as "ripple and noise." Here, the ripple stands for the periodic ac content riding on the dc-output voltage and is similar to the oscillator frequency plus its harmonics. The noise indicates the broadband noise of the dc output. Examine this specification carefully: The condition under which it was specified may have included a 20-MHz lowpass filter that caused significant attenuation at the higher frequencies. If you evaluate the output of the converter with a 350-MHz oscilloscope, ripple and noise appear much larger than specified.

This noise requires appropriate filtering not only for the output, but also for the inputs. Strictly speaking, you don't need to filter the supply voltage for the dc/dc converter, but you do have to block the noise from the converter to prevent the high-frequency switching noise from migrating into the main power supply. Watch out for the term "reflected ripple current" in the specifications sheets of those dc/dc modules. The LC-type lowpass filter arranged as a pi-filter (C₄₅, C₄₆, L₃, C₄₇, and C₄₈) minimizes the magnitude of the reflected ripple current produced by the dc/dc converters. The 0.1-µF ceramic capacitor shunts high frequencies to ground, and the polarized 22-µF capacitor, C₄₇, functions as a tank capacitor to supply a high-transient current for the switching process.

To reduce the ripple and noise of the 15V supply lines, you can use LC lowpass filters. Only inductors L₄ and L₅ are located at the outputs of the converters. The filter capacitors are distributed over the entire board and are actually the bypass capacitors. You can use the 10V output voltage directly as the positive-supply rail for buffer amplifier IC₁₃. Because the output voltages of the dc/dc converter are unregulated, you can add a standard 78L05 regulator to supply 5V for the ADC. This process improves the ADC's power-supply rejection, thus maintaining a stable and reliable function for this sensitive IC.