Design Ideas: August 15, 1996
The bidirectional circuit in
Figure
1 translates TTL to shifted ECL (SECL). There are currently no IC's
available that perform this type of level translation. SECL levels correspond to
either ECL or PECL referenced to a VCC of 2V and a VEE
of -2.5V. You frequently encounter these levels in situations where the outputs
of the ECL logic terminate through 50(ohm) directly to ground (most lab
equipment, for example) instead of the nominal -2V (ECL) or 2.5V (PECL) VTT.
To translate from TTL to SECL, each TTL data line connects to one of the control lines of a 74HC4053 analog switch with pull-up resistors to VCC. The pull-up resistors ensure that the TTL levels are compatible with HCMOS. When R/W is high and NSTROBE is low, the decoded control latches the translated TTL data bus into the 100E175. Note the reverse polarity of Z0 and Z1 on IC3, which inverts the signal. Powered from the SECL supplies, an E-Lite 100EL04 gate (IC12) provides SECL low- and high-reference levels; you can replace this gate with any unused SECL gate in the design.
The SECL low and high voltages connect to the analog- switch inputs of the 74HC4053s. The digital supplies of the 74HC4053s connect to standard TTL power, and the negative analog supply is the SECL VEE of -2.5V, which adequately ensures proper operation, even with switching transients. The 100E175 latch provides storage and eliminates the switching transients from the translated data bus. SECL data EDO[0 to 7], along with parity, appear at the latch's outputs.
Translation from SECL to TTL requires both R/W and NSTROBE to be low. The decoded output of IC12C translates into a SECL clock signal that loads the SECL data bus EDI[0 to 7] into the 100H607 PECL-to-TTL translators. The SECL supply powers these translators. The output of the 100H607s swing from approximately -2.2V (low) to 1.8V (high), ensuring an adequate swing to the control inputs of the 74HC4053s. The outputs of these analog switches swing from approximately 0 (low) to 2V, which is sufficient to drive the inputs of the 74LS244. Low levels at R/W and NSTROBE enable the outputs of the 74LS244, and the translated SECL data appears at TD[0 to 7]. (DI #1911)