Design Feature: September 2, 1996

EEs need offer no apology for skepticism about built-in self-test (BIST). Disbelief is a natural reaction to a technology that zealots have proclaimed to be on the verge of revolutionizing electronics for nearly a generation. Nevertheless, BIST's time is finally arriving. Although many designers have yet to conclude that BIST makes economic sense for them, those who adopt the technology often discover unexpected benefits. In many cases, these benefits result from the structured design approaches that certain types of BIST enforce.

BIST is a mainstay in a few areas: military and aerospace equipment, fault-tolerant and continuous-availability computers, and telephone-central-office equipment. You might think that BIST would be popular in many reasonably expensive products that are subject to environmental extremes, particularly shock and vibration. Thus, you might expect to see BIST in laptop PCs, automotive electronics, and high-end personal-communication devices. To date, however, the last three areas have remained decidedly cool toward BIST.

One of the problems with discussing BIST is defining the term. To certain test professionals, "BIST" means something far more restrictive than it does to other EEs. Most EEs would say that an IC performs a BIST if, on command, the IC isolates itself from surrounding devices, runs functional tests on itself, and reports to the outside world whether it is good or bad. Because the tests are functional, however, some people in the test community argue that such a chip, though it performs a built-in test, does not perform a built-in self-test. Those who hold this view assert that, to qualify as using BIST, a chip must test itself using internally generated or stored vectors.

Nevertheless, most test experts take a much broader view. According to these experts, BIST can use functional tests, random vectors, or deterministic vectors. These experts also hold that BIST can apply to ICs, multichip modules, pc boards, subsystems, and complete systems. Moreover, a unit that is testing itself can take itself out of service (off-line BIST) or can continue to function, albeit at somewhat-reduced speed (on-line BIST).

Test and EDA people make a major distinction between memory BIST and logic BIST. Of these two types of BIST, memory BIST is the more highly evolved and the more widely accepted. But even memory BIST is not universally accepted. Memory BIST is becoming popular for testing memory embedded within complex ASICs. This memory can be masked ROM, EPROM, EEPROM, or RAM—most often, SRAM—though, sometimes, DRAM (Table 1).

No commodity memory parts use BIST, however. So far, makers of such devices have not justified the extra silicon that BIST circuits would add. You can get an idea of memory-BIST area requirements from Figure 1. Bear in mind, though, that not all of the pictured ASIC's memory-test circuits test memory within the IC; some of the circuits test external memory chips.

BIST is useful for embedded memory, because, as ASICs become more complex, propagating test vectors inward from the pins to the memory structures becomes increasingly difficult and time-consuming—some would even say impossible. And, similar problems exist with propagating test results from the memory structures back to the IC pins. Moreover, many complex ASICs contain multiple memories, which BIST can often test simultaneously. When you test these memories by applying vectors from an external source in an automatic test system, you must usually test each memory separately. This approach consumes valuable time on expensive test equipment.

Another problem with using externally applied vectors for testing large embedded memories is the need to repeatedly reload the tester's vector or pattern memory. With many memory-test protocols, pattern depth is more than directly proportional to memory size. With large memories, vector sets can be much larger than the tester's pattern memory, forcing the tester to repeatedly fetch additional information from a hard disk. These fetches considerably slow testing and increase test costs by reducing the throughput of expensive test systems.

An alternative is algorithmic pattern generation. Few ASIC-test systems offer this option, however. And, when the option is available, it is expensive. Additionally, many ASIC testers can't test high-speed memories at full speed, because the size of the system requires driving very fast signals down long cables. BIST approaches usually have no such limitations, because the distance between the test circuits and the elements under test are microscopic. So, BIST not only is faster, but also often catches timing faults that externally applied vectors fail to detect.

A major use of memory BIST is in IC manufacturing. Except in ICs that contain small amounts of memory, enough memory structures contain defective cells that it makes economic sense to add redundant cells to the chips. IC manufacturers increase yield and save devices from the scrap heap by substituting redundant rows or columns of cells for rows or columns that contain defective cells. The companies use a variety of proprietary processes to make the substitution. Using memory BIST to identify bad cells is a key factor in holding down the cost of complex, memory-intensive ASICs.

BIST has many roles

Production-IC testing is scarcely the only area in which BIST offers potential savings, however. BIST can provide benefits in a typical large commercial system, such as a fault-tolerant computer, a telephone central office, or a multimillion-dollar automatic-test system. These benefits can emerge in preproduction design verification, module test, board test, subsystem test, final system test, initial system installation, routine maintenance, field-repair depots, and failure-analysis laboratories. In these laboratories, engineers and physicists look for failure mechanisms that point the way to manufacturing-process improvements.

Before you base a system-level test protocol on BIST that was designed to assure the quality of unpackaged IC chips, however, you need to know whether the test is likely to catch enough system-level failures to justify its use. The types of failures that are common in unpackaged dice are not necessarily those that affect higher level products.

If you wonder how you can have confidence in BIST circuits, understand that BIST is less likely than other testing technologies to tell you that a defective unit is good. In any unit of even moderate complexity (that is, an IC, a module, a board, or a system), the number of possible defects is staggering. Therefore, the probability of compensating defects resulting in an erroneous report of a good device is minuscule. You can't extend this argument to say that it is easy for a good device to tell you that it is bad. If a device that is "good" tells you that it is bad, it is bad—by definition.

A common misconception about BIST—even among some EDA-tool suppliers—is the idea that BIST provides only a go/no-go indication of whether an IC or a larger unit is functioning. Even for ICs, BIST can provide much more detailed information, often localizing the failure to a defective gate and indicating the nature of the fault. Although fault localization slows testing too much for use in production, properly designed and implemented BIST lets failure-analysis engineers pinpoint faults.

Area-overhead controversy

Another controversial subject is the area that BIST structures occupy on ICs. To listen to some BIST partisans, BIST structures take up so little room on a die that you are foolish to concern yourself with area requirements. Meanwhile, others say that, in combinatorial-logic designs, BIST's area requirements often top 30% of the area that functional circuits occupy. To understand the large discrepancy, you need to dig a little deeper.

Experts who quote logic-BIST overhead of much lower than 0.5% of a die's total area are usually talking only about the area occupied by the BIST controller, a logical block that BIST tools can synthesize in about 400 gates. On a chip containing 100,000 gates, 400 gates do indeed represent only 0.4% of the area. However, the BIST controller is scarcely the only circuitry that must exist on a logic chip to implement BIST.

The argument that a 0.4% area penalty is accurate is based on the assumption that, even without BIST, the IC would use internal scan, a design approach that, for test purposes, turns sequential logic into combinatorial logic. Thus, for designs that already use full scan with externally applied test vectors, the conversion to BIST can involve few extra gates. Note also that scan-based design is an issue only for logic BIST; there is normally no comparable area-overhead issue with memory BIST.

BIST advocates also quickly point out that BIST does a better job of testing than do externally applied vectors. With logic BIST, just as with memory BIST, the distances between the test circuits and the circuitry under test are minuscule compared with the distances on large IC-test systems. The small geometry means that, unlike test systems' pin drivers, BIST circuits need not drive fast edges down long cables. Thus, BIST can enable at-speed testing of very fast circuits. With externally applied vectors, such testing is often impossible or prohibitively expensive. As IC feature sizes shrink, faults that are detectable only through at-speed testing represent an increasing percentage of faults.

Where BIST is free

On certain logic ICs, even if you do count the gates that implement internal scan as part of the BIST overhead, BIST requires no extra silicon. The devices for which this claim is true are pin-limited gate-array designs. On such I/O-limited devices, it is common to be able to use no more than 60% of the gates for the functional circuitry. Gates that would otherwise be unusable are available to implement internal-scan and BIST functions.

In such cases, BIST partisans assert, not only is BIST free, but designing a part that uses logic BIST takes less time and costs less than designing an equivalent part without BIST. According to people who have designed ICs using logic BIST, BIST saves money even when you add the cost of the EDA tools or the licensing fees for the BIST structures. The reason is that the structured-design methodology that logic BIST enforces cuts design time, and the BIST structures on the chip reduce the time needed to debug the first silicon. Moreover, because the tools that add BIST to the design generate and embed the test patterns, you save the time that generating external vectors would require.

These same partisans insist that, from a design-time viewpoint, the case for memory BIST is even stronger than that for logic BIST. Implicit in the argument that logic BIST saves time is the assumption that organizations that design ICs are already familiar with internal scan. Estimates of design time saved by using logic BIST don't account for the time EEs spend learning how to produce scannable designs. With memory-BIST tools, however, no learning curve exists. In most cases, you simply run the tool and out pops an RTL design incorporating BIST. Moreover, unlike many design-for-test (DFT) EDA tools, which take hours or days to complete their jobs, memory-BIST tools do their work in minutes.

When you add improved test quality and reduced test cost to savings in design time and design cost, the arguments for BIST start to sound unbelievably alluring. Before you dismiss such claims as mere vendor hype, understand that the sources are not just tool suppliers, but also users of BIST tools. Still, these users do not represent a broad spectrum of electronics companies. Significant by their absence are makers of consumer electronic products, PCs, graphics adapters, and automotive electronic products.

Although Lucent Technologies is a supplier of BIST tools through its Bell Laboratories Design Automation business unit, the company—until recently, part of AT&T—is also one of the world's largest BIST users. Since 1988, AT&T and Lucent have designed and produced more than 400 ICs that use memory BIST. Other IC manufacturers can now license from Lucent the presynthesis RTL core libraries those ICs use.

Too good to be true

Because the too-good-to-be-true aspect of BIST does not play well to EEs' natural skepticism, BIST companies are well-advised to go slowly in peddling their wares. Instead of offering BIST as a panacea, BIST suppliers may urge designers to add BIST techniques to their arsenals. Designers who apply BIST in a limited portion of one chip design are likely to recognize the advantages of the technology and use more complete implementations in successive designs. As one BIST supplier puts it, designers will recognize that IC chips that use BIST are like potato chips; one chip is never enough.

Cadence Design Systems believes that widespread confusion about the pros and cons of various DFT techniques presents a business opportunity. Cadence's consulting unit stands ready to advise chip designers about which tools and techniques are most appropriate for particular designs. Cadence feels that most complex ICs should incorporate multiple test methodologies. For example, a chip might use BIST for its memory structures but might use internal scan with externally applied vectors for testing its random logic.

Something that is almost a least common denominator of BIST technology is the IEEE-1149.1 test-access port (TAP). Although chips can provide access to BIST functions in other ways besides an IEEE-1149.1 TAP, the TAP is the most popular means of access. Curiously, BIST access is part of the IEEE-1149.1 because the standard's designers realized that adding the feature was easy. Because of the TAP's pervasiveness in BIST, the "For free information... " box lists several IEEE-1149.1 suppliers. Texas Instruments and National Semiconductor supply IEEE-1149.1 interface chips. Asset Intertech and Corelis supply hardware and software test-development tools.

You can reach Senior Technical Editor Dan Strassberg at (617) 558-4205, fax (617) 928-4205, e-mail ednstrassberg@cahners.com

References

1. Aadsen, HR, HN Scholz, and Y Zorian, "Automated BIST for regular structures embedded in ASIC devices," AT&T Technical Journal, May/June 1990, pg 97.
2. Agrawal, VD, C J Lin, PW Rutkowski, S Wu, and Y Zorian, "Built-in self test for digital integrated circuits," AT&T Technical Journal, March/April 1994, pg 30.
3. Zorian, Y, "Built-in quality assurance," Transactions of the Third International Conference on the Economics of Design, Test, and Manufacturing, May 1994 (available from IEEE Computer Society, Los Alamitos, CA).

Acknowledgments

Tom Eberle and Joe Wagovich of Lockheed-Sanders and Mike Bergenthal of Texas Instruments provided much valuable information for this article.