Out in Front: September 2, 1996
Motorola's new MPC801 is a toned-down version of the company's MPC860 PowerPC-based µP. In creating the general-purpose 801, Motorola designers removed several of the 860's peripherals and cut the cache size in half. The resultant processor is a moderately priced device selling for $29.95 and $37.50 for the 25-MHz and 40-MHz versions, respectively (10,000).
In addition to containing an embedded PowerPC core, the MCP801 contains a system-integration unit (SIU) and a serial-interface block. The core comes with a 2-kbyte instruction cache and 1-kbyte data cache, each with its own eight-entry MMU. The MMUs support page sizes of 4, 512, and 16 kbytes, as well as 8 Mbytes. The caches are two-way set associative with 4-byte cache lines and software lockability on a line granularity.
The SIU provides a memory controller, power-management functions, timers, and a real-time clock. The memory controller supports up to eight memory banks with glueless interfaces to DRAM, SRAM, EPROM, flash, SDRAM, and EDO. The memory controller also supports dynamic bus sizing for 8, 16, and 32 bits. The serial-interface block includes two full-duplex UARTs with IRDA, I2C, and SPI support.
—by Markus Levy
Motorola, Austin, TX. (512) 891-3823.