| FIGURE 1 |
 |
| The quest for performance has turned away from µPs and toward the bandwidth to memory. Hal turned to a four-way set associative cache to maximize memory throughput relative to the direct-mapped level-2 caches that most systems use. |
back |
| FIGURE 1 |
|
| The quest for performance has turned away from µPs and toward the bandwidth to memory. Hal turned to a four-way set associative cache to maximize memory throughput relative to the direct-mapped level-2 caches that most systems use. |
back |