Design Feature: September 26, 1996

Digital signals must quickly and predictably cross through the logic threshold, or "forbidden zone," so that you can characterize the resulting signal at the next component as either a one or a zero at a predicted time. A signal that oscillates across a logic threshold can cause multiclocking or illegal signal gating. A signal that overshoots to too positive or too negative a voltage can cause physical damage to the components. A signal that is not driven strongly enough at its source might not be able to drive the appropriate dc digital values.

A designer must also worry about secondary effects of transmission-line behavior, including crosstalk, which is active signal coupling to nearby unassociated signals, and EMI. You cannot address these problems by simulating only critical nets, because even simple nets may contribute to fast datapath-hold problems.

To solve coupled-transmission-line and signal-integrity problems in large high-speed digital systems, you need an accurate simulation mechanism that can provide analog waveforms showing the behavior of the line at any node. These waveforms must accurately model the driving devices and the wires and should allow for experiments to simulate proposed solutions to located problems.

Fast simulation allows you to iterate the design. You probably must use a behavioral device-modeling approach for this simulation, because the simulation can be faster than Spice-like simulation without sacrificing accuracy.

Solving coupled-transmission-line and signal-integrity problems also requires a simulation system that targets the large-system problem of setting up and analyzing the simulation data. It must automatically extract the network-circuit topologies from pc-board layout and calculate the line impedances and velocities. It should scan the resultant analog waveforms for illegal results and flag errors for easy identification and repair. The system must then send the results back to the design itself for correcting circuit-termination, layout, placement, or, perhaps, basic digital-design problems.

In transmission-line simulation, you use the simulator early in the design to plan the critical routes and later in the design to iterate to a correct physical layout solution (Figure 1). The clock is often the tightest timing section of the design, and signal integrity on a clock net is essential because clock-timing circuitry cannot tolerate double logic crossings, as a data line can.

Using simple assumptions about network length and impedance and the known values for the drivers and receivers, you can devise a suitable clock-network-routing strategy. You must select a distribution topology, depending on whether termination is necessary and, if so, what values you should use. Also, you must determine the most efficient driver technology (FAST, ABT, etc). You must also determine what clock-delay skew ranges you can expect.

Use the timing-analysis tool before or with placement. Given any part placement and a simple algorithm for signal time of flight, timing analysis can locate datapaths that cannot meet timing specifications, regardless of the route they use. These parts are simply too far apart for the propagation speed in the media to allow signals to meet proper setup constraints. Some timing tools can suggest workable or even optimum placements. Some routers can accept timing-based placement criteria. A benefit of this approach is that the design is now prepared and ready for more accurate pin-to-pin delay information that will come from the postroute signal-integrity analysis of the system.

Using timing constraints, you can set up mandatory placement or at least strong constraints on the placement before placement and routing. You can also establish other general design rules for the pc-board route before the route occurs. Use sample representative wire runs and driver technologies to calculate minimum line spacing or maximum parallel routes from a crosstalk/noise-margin standpoint. A design's noise budget usually determines the maximum allowable crosstalk. Some new routers allow this maximum parallelism input as a direct control of the router.

After you determine a termination strategy for the clock nets, you can also feed this information into the router. A termination strategy implies a pin-net ordering, because the termination must fall on the proper end of the net. The other important input to the router is allowable critical-net length, which should come from the initial timing simulation. Many vendors are developing timing-based placement-and-routing technologies.

Postroute analysis should be as fast and automatic as possible. It should automatically create the simulation database from the layout database. The main task of this extraction is the automatic creation of the transmission-line topologies and wire models for use during the transmission-line simulation. If your signal-integrity simulation package cannot extract data from your layout package, you cannot implement this step.

At this point, you can run a complete transmission-line simulation of the digital nets on the board and locate potential signal-integrity problems using the simulation software. This allows you to easily find and repair the problems in the design.

It's important to have a highly accurate, easily simulated model when you're constructing the topologies and wire models from the pc-board-layout database. A common and accurate assumption for transmission-line simulation is the transverse-electromagnetic (TEM)-mode assumption, which states that the electromagnetic field that surrounds a trace is uniform in the axial direction. This assumption holds true only for conductors that have uniform cross-sectional shape and are significantly longer than they are wide (typical in pc-board systems).

Using the TEM assumption, you can use cross-sectional, 2-D field extraction techniques to build accurate per-unit-length models of the transmission-line segments, of single and coupled systems. The TEM assumption has frequency limitations, and future simulation tools may have to resort to full-wave calculation techniques.

With an accurate analog simulation, you can automatically detect many aspects of illegal behavior. If receiver logic thresholds are known--and they must be for accurate pin-to-pin delay calculation and noise-margin budgeting--then you can locate possible multiple-threshold crossing or forbidden-zone, nonmonotonic behavior. The part's data book usually states the legal operating range of the part. If you know this range, then you can calculate maximum overshoot regions.

Termination and crosstalk are key

Improper termination or too much dc load on a line can prevent the driver from driving the line to switching voltage. Simulation can also detect improper termination. As designers increasingly use transmission-line-simulation tools for standard components, the data describing these components changes to reflect this error detection. Expect vendors to describe parts with maximum overshoot in a time and voltage manner and receiver thresholds in a pulse-filter manner. You can also expect the receiver thresholds themselves to tighten up as CMOS and 3V components begin to dominate the market.

Automatic detection of crosstalk is also an important part of the error-detection phase of signal-integrity simulation. In this case, "crosstalk" is the deviation of the voltage at a given receiver on a passive network from dc operating point. The actual energy coupled to a passive net is not of direct concern unless that energy affects the signal at the receiver. This definition implies that the position of the receivers and drivers and the state of the passive driver are critical to the amount of crosstalk that any receiver detects.

To find the worst-case crosstalk situation, you must simulate every combination of drivers on both the active and passive nets. Figure 2 shows the waveforms at a single receiver in four separate simulations. This passive net is a bidirectional net with two possible drivers at different locations on the net. Two drivers and two states make for four simulations. The figure highlights the worst-case state for this active net.

To calculate the maximum crosstalk that appears at any receiver due to all possible coupled-driver combinations, make some simplifying assumptions about the expected coupled-driver patterns. In theory, the combination of signal-integrity simulation with an exhaustive operational simulation could lead to the relative switching times of all devices. In practice, the exact transition time of all drivers correlated to all other drivers is unknown because of component internal-timing skew.

One way to handle this problem is to add the worst-case crosstalk from each coupled line either directly or using root sum of squares or another averaging function. This approach most likely yields either a pessimistic or a statistically correct result. Although this result may be nonideal, its alternatives can be prohibitively expensive.

One relatively new approach uses the global slack time that a timing-analysis tool generates. In this case, "slack" describes the relative arrival time, in timing windows, of all signals arriving at a latch or register. You use this approach to calculate that part of the crosstalk waveform that cannot contribute to the transitional setup-and-hold window of the latching device. This method allows a timing window to gate worst-case crosstalk and a less pessimistic result. This method also amplifies the cross connections of timing-analysis and signal-integrity simulation.

Once you locate the problems, you must repair them. Removal of signal-integrity artifacts is something of an art, and a certain amount of experience is helpful--if not essential. A signal-integrity tool with good what-if capability can help by quickly predicting the effects of your proposed changes. The nature of those changes, however, still depends on understanding the basis of the signal-integrity problem the changes are addressing. Table 1 summarizes many typical signal-integrity problems and their probable cause and likely solution.

Networks with signal-integrity problems show how you can approach problems and repair. In Figure 3, the automatic detection software flags the target receivers as having excessive overshoot. As Table 1 shows, one way to address overshoot and ringing is to terminate the problem line near the problem area. Figure 3 shows a simple parallel termination to 0V using 100, 75, and 50[ohm] resistance values. Even a simple termination scheme such as this involves a trade-off among effective damping; dc-voltage level; and dc levels, which relate to power dissipation. You could use a more complex termination, such as a voltage-divider pair, to terminate in an effective Thevenin voltage and resistance.

The signal-integrity software must provide you with an easy mechanism for what-if experimentation. You can address unwanted crosstalk by terminating the passive line, changing the technology of the active drive, or changing the route of the signal (Figure 4). (The coupled noise is the small signal at the bottom of each waveform.)

Crosstalk is the deviation from dc of the passive receiver, so your design should absorb the crosstalk noise at or near the passive receiver and not change the active signal at all. You can change the technology of the active drive. Because crosstalk is a direct function of the rise time of the active signal, slowing that rise time can decrease crosstalk and often improve signal integrity on the active line. Many new-technology bus drivers are pin-compatible with older technologies, so using rise-time-controlled components can be a relatively easy and inexpensive design change.

Addressing crosstalk by changing the route may be the hardest change to make, because it forces a change in the entire pc-board-layout database.

Often, straight dc termination is unfeasible because of dc-current and power-consumption considerations. A solution to this problem is to use ac termination. Figure 5 shows the waveforms at a single receiver using three ac-termination values. AC termination uses a resistor and capacitor in series to eliminate the dc path from the circuit.

The trade-off with ac termination devices is that they may take up more room than do dc resistors. Also, they are susceptible to charging effects that can affect the low and high state operating points at high clock frequencies. Simulate your ac-terminated line at full frequency for several cycles.

Fast simulation of transmission lines is possible only with the use of behavioral-device models. Because behavioral models depend on abstracting all important features or behaviors from the structural models, they can be as accurate as structural models over the test region, in this case, transmission-line phenomena. At the same time, because the behavioral approach ignores much of the information within the structural model, behavioral models can be easier to write and faster to simulate.

Another benefit of behavioral models is that component vendors can specify them without revealing proprietary information about the actual construction of the output devices. This security is important to IC manufacturers and encourages them to release models in a behavioral-modeling format (see box, "IBIS supports behavioral-model effort").

You should not blindly trust modeling data or simulations. Ideally, you would compare each incoming model with some physical test system to verify accuracy. If physical measurement is impossible, then you may be able to test the model against a proven analog simulation model, such as one using Spice or the equivalent.

When you compare simulation results to physical measurement, keep a few things in >=>=mind. The measurement you make is only as good as the equipment making the measurement. Measuring a subnanosecond edge requires an accurate scope and probe, plus a good knowledge of the probe-connection technology and loading.

Once you make the measurement, consider the accuracy of the test-circuit parameters. For most IC components, the rise time and drive strength are within 5% of nominal. Dielectric constant may be within only 20%, and trace thickness and width are within 5 to 10%. This wide skew in possible input parameters makes it difficult to exactly simulate a given system unless you carefully characterize the system and base the simulations on that measurement.

By looking for key features, however, you can find an acceptable level of correlation using typical models compared with any in-range system. If you can't make actual measurements, at least ensure model accuracy by comparing results to expected dc values and transition times. One good test for the accuracy of a behavioral-modeling simulation is to test the simulation of a complex behavioral device, such as a rise-time- or slew-rate-control device.

Signal-integrity simulation is not free. Before you start on this methodology, weigh the costs against the benefits. Although the I/O Buffer Information Standard (IBIS) is growing in popularity and use, most IC components are still unavailable in this format. Some additional models are available in Spice, which you can easily convert to IBIS, but parts of the design require original model development. The maintenance of the part library is one of the largest costs of signal-integrity simulation. Fortunately, behavioral models are easier to write and verify than are Spice or other structural models.

For most signal-integrity simulators, you must translate and extract the pc-board-layout database. This process has some special activities for each design. You can save time if you take the signal-integrity simulation into account before pc-board layout and format your pc-board database accordingly. For example, you may want to use pin numbers instead of names to be consistent with the IBIS model. Once you simulate the database, an engineer must go over every error and decide whether and how to fix the problem. Depending on the nature of the problem, this process can be time-consuming. However, you'll probably spend even more time later when the design does not work.

You must also consider the cost of the signal-integrity software, which ranges from $10,000 to $50,000 for single-user systems. The benefits are fewer design turns, no prototypes, higher yield and quality, and quicker time to market.

After completing the simulation exercise with your circuit board, you can perform several other steps to ensure the quality of the entire system. You can use the signal-integrity-simulation environment for a board to plug into similar models of backplanes and other boards to test system-configuration and -compatibility issues. Software products are now emerging that can use the signal-integrity waveform information and other input to perform EMI predictions, simulating open-field test conditions and locating EMI hot spots.

As high-speed design becomes more commonplace, the need grows to automate the entire signal-integrity and timing-design process. This need was especially evident, for example, with the recent Pentium and PowerPC chip-set designs. Users that had previously relied on simple rule-based design-and-route found themselves with marginal designs and desperately needing signal-integrity and timing but without the budget or know-how to use such tools.

A trend exists toward AI-assisted signal-integrity simulators, or "correct-by-design" place-and-route systems. These systems are still in their early development and have not yet proven their effectiveness.

(This article is adapted from the EDN-sponsored portion of the Design SuperCon show. For a reprint of the original paper, contact Quad Design at (805) 988-8250.)

Jon Powell is a senior scientist at the Quad Design Group of Viewlogic Corp, where he designs engineering software for EDA applications. He has worked at Quad Design for nine years and holds bachelor's and master's degrees in electrical engineering and computer science from the Massachusetts Institute of Technology (Cambridge, MA).