Design Feature: September 26, 1996

  Four years ago, Lattice Semiconductor introduced the first nonvolatile in-system programmable (ISP) device, the ispLSI 1000. Since then, the number of companies that offer erasable PLDs with ISP has grown to five. Most companies that produce these devices say they will soon introduce only high-density PLDs with ISP. These companies claim that designers consider ISP a must-have capability. According to the manufacturers, if designers aren't using ISP now, then they will be using it in the near future. The reason for the fast growth and wide acceptance of ISP devices is no mystery. ISP devices provide tangible benefits during product development, manufacturing, and field support.

Prototyping benefits

  At the design-development stage, you can use the same ISP device package for your prototype system that you will use in production, and you can solder it to the pc board without a socket. ISP allows you to program the device in the system (numerous times, if necessary) until the design functions correctly. The electrically erasable and flash technologies used for the ISP devices let you reprogram devices in either a few seconds or a few minutes, depending on the devices and the programming methods you use. Even before ISP, designers were reprogramming devices or programming new ones to correct design errors. ISP makes the process simpler and faster. You don't have to use special sockets for surface-mount devices or remove them for programming.

  Designers that work with PLDs use a wider spectrum of design methodologies than ASIC designers typically use. ASIC designers strive for and often achieve first-pass success. Economic consequences make it imperative. First-pass success takes careful, deliberate work, including full simulation of the device and the system. Some PLD designers use the same methods with the same dedication to first-pass success as ASIC designers. Indeed, some designers perform both types of design. Other designers take a shoot-from-the-hip approach, using little, if any, simulation. Most designers probably fall somewhere in between.

Program/erase cycles

  All of the ISP-device families provide at least 100 program/erase cycles, and some guarantee 10,000 cycles (Table 1). To get your design right, 100 attempts should be ample, even for a shoot-from-the-hip designer. If it isn't, you would probably benefit from taking a more thorough approach to simulation, rather than migrating to a PLD family that offers 10,000 program/erase cycles.

  The flexibility to program and reprogram a device in-circuit even lets you create a board design and send it off for layout and fabrication as you work out the details of the logic that goes into the PLD. Paralleling your logic- and board-design efforts lets you work with a very aggressive schedule, potentially shortening your time to market.

  Sometimes the paralleled-design approach succeeds, but you have to be aware of the pitfalls of assigning a PLD and fixing the pins before designing the logic that goes into the PLD. There are three potential problems: pin fixing, logic capacity, and speed.

The pitfalls of pin fixing

  Pin fixing, or "pin locking," is when you assign pins on a device to specific I/O functions and don't allow them to move later in the design process. When you assign pins without regard for the logic operations being performed by the device, pin fixing can get you into trouble. Some architectures offer extreme design flexibility. For those devices, pin assignments are unimportant, except for dedicated functions, such as input-only pins, global clocks, and resets. Logic can move to different macrocells on the chip to accommodate pin assignments, or routing resources can connect the logic function with the selected pin. Devices with less pin-fixing flexibility can suffer from reduced performance or from a complete inability to route if you use pin fixing with nonoptimum pin assignments.

  ISP devices that can accommodate design changes when pin assignments remain fixed can save you time and money by eliminating the need to redesign a pc board. Because the ability to make design changes when pin assignments remain fixed is so important, it's not surprising that each manufacturer of ISP devices claims its architecture supports pin fixing. Although every PLD architecture accommodates some degree of logic change after you lock down your pin assignments, most architectures have limitations in the magnitude of the changes they can accommodate. Examining the architectural details of the device families you are considering should give you some subjective feeling for the flexibility in regard to pin locking.

  The more conservative approach to pin locking is to design the logic for the PLD and then to create a pin assignment for the device from that logic implementation. Then, you can lock the pins and have greater confidence that incremental changes to the design will still work with your original pin assignments.

  If you select a device with insufficient logic resources, the problem won't be fixed by changing pin assignments. You need a device with more logic resources. Some manufacturers of PLDs provide a simple solution to this problem by providing a range of logic capacities for each package size. By selecting a device that has more or fewer macrocells in the same package, you can alter the logic available later without a new design layout.

  A range of logic capacities within the same package means you can move not only to a more expensive device with more logic resources if necessary, but also to a less expensive device with fewer logic resources if it turns out you need fewer macrocells than you originally thought.

  If the device you select isn't fast enough, you may be able to change to a higher speed device. Pin fixing, logic capacity, and speed can also end up working together.

  For example, you can overcome pin-fixing limitations by taking a second pass through additional logic resources, but the result may be too slow for your application. Changing pin assignments can help you regain lost speed and reduce the logic resources you need.

  ISP offers attractive features during the design and prototyping stages of a system. It can speed the design process, and it can bail you out of problems after you have hardware. If you are lulled into complacency by being able to reprogram your way out of any mess, you will eventually be burned. The best approach is a conservative one until you gain the experience to know what changes you can get away with.

ISP simplifies manufacturing

  ISP devices also let you make significant changes to the manufacturing process. For some companies, the manufacturing advantages of ISP devices are the major economic attraction of using them.

  Without ISP, a company must take incoming devices and program, label, and hold them in inventory until ready to assemble on a pc board. Each logic design for a particular PLD must be programmed separately and kept in separate inventory. High-density devices using delicate packages, such as 100-pin PQFPs, are easily damaged unless the company can justify expensive automatic handlers for programming the devices.

  ISP eliminates these steps. ISP devices are essentially treated as any other device going onto the pc board. You program ISP devices after they are mounted on the board and just before board test. Design revisions do not result in wasted parts or reprogramming and relabeling. Fewer manufacturing steps not only save time, but also result in fewer opportunities for errors.

  Removing additional programming and inventory steps reduces handling of the delicate packages, resulting in fewer bent leads and scrap devices. You also reduce the potential for electrostatic damage with less handling. Although you can get around the programming and extra-handling problem for non-ISP devices by buying preprogrammed devices through a distributor that offers programming, you still have extra inventory and rework problems whenever you make design changes.

  Changing programming from its own dedicated step in the manufacturing process and combining it with the board-test function does have some implications that are important to consider. Instead of programming the PLDs on a dedicated programmer, the programming operation takes place on a board tester or a boundary-scan IEEE 1149.1 JTAG tester.

  Board testers, such as those from GenRad (Concord, MA), Hewlett- Packard (Santa Clara, CA), and Teradyne (Boston), are much more expensive than device programmers. It is important that programming times remain short to avoid significantly reducing the throughput of the board tester and tying up expensive equipment. Typical programming times on board testers range from a few to tens of seconds, depending on the device architecture, the size of the device, the programming method you use, and the speed of the equipment performing the programming. This programming time adds to whatever test time the board itself requires.

  If you must program more than one device on a pc board, the programming times for the individual devices are added together, thus increasing programming time. Advanced Micro Devices (AMD) and Lattice Semiconductor both offer methods to reduce programming times when you program multiple devices on the same pc board.

  AMD offers a parallel-programming scheme. It requires approximately 0.5 sec to download the programming data for each device on a pc board and approximately 4 sec for the programming cycle that is common to any number of devices. The net result is that each additional device on a board adds only about 0.5 sec to the complete download and program-cycle times.

  Lattice Semiconductor offers what it calls a "turbo-programming mode" that lets you quickly program multiple devices on a board. The programming lines of all the devices are daisy-chained, and the programming time is almost the same as the time for programming the largest individual device in the daisy chain. For pc boards with many ISP devices, the savings in programming time is substantial.

IEEE 1149.1 JTAG testers

  If additional time on an expensive board tester for programming is undesirable, you can program the devices using other, lower cost methods; however, they require an added manufacturing step. You do not need a complete board tester for the in-system programming. You can program the devices from a PC using a suitable programming cable and software or with an IEEE 1149.1 JTAG tester. A JTAG tester is much less expensive than the typical bed-of-nails board testers, and it can program most ISP devices.

  You can also program the ISP de-vices using a PC with a suitable interface card and programming cable. PCs tend to be slower because they transfer data at a slower rate, often considerably slower than programming with a 10-MHz IEEE 1149.1 JTAG tester. PCs can stretch programming time to minutes per device. PC-programming methods are suitable for prototype development and production of relatively low quantities. Higher quantities tend to favor the JTAG systems or complete board testers.

  One of the concerns in moving from separate programming and test-before-soldering devices to a pc board and programming after the device is soldered into the pc board is yield. If devices don't program or somehow fail after in-system programming, then you have to remove the device from the pc board and replace it. For ISP to work without expensive reworking of pc boards, you need very high yields after programming. Manufacturers of ISP devices report high programming yields. For high-volume manufacturing operations, you may want to check directly with PLD manufacturers for specific programming yields.

  Another interesting possibility open to your design and test strategy when you use ISP devices is the possibility of programming the device twice. The first configuration is designed to aid in your board-test operation. The second program configuration is for your product's primary application. Although the extra program and erase cycle adds to the overall test time, the extra program cycle can prove beneficial for testing some otherwise-difficult-to-test part of your product.

  You don't have to limit using additional configurations to your manufacturing-test operation. You might want to take advantage of the reprogramming capability of ISP devices in the field, too. Reprogramming falls into one of two types of operations. The first is reprogramming that is part of the system design. In this case, the reprogramming capability is built into the system and made transparent to the end user.

  For example, you might design a system that is able to work with a variety of communication standards but can use only one communication standard at a time. The end user could reprogram the device in the field for compatibility with a select communication standard.

  When you use reprogramming as a design feature, then the design is defined up front. You can test the different designs to be sure things such as a lack of logic capacity or pin fixing don't cause a problem.

  It is possible for some applications that take advantage of reprogramming to require more than the 100 program/erase cycles offered by some of the devices shown in Table 1. Other devices in Table 1 are guaranteed for 10,000 program/erase cycles. If you need more than 10,000 program/erase cycles then you need to consider SRAM-based PLDs.

  The other type of reprogramming is not defined, or at least not completely defined in the original product. You may plan to upgrade your product to add a feature later, but that upgrade isn't completely designed when you release the first product to production. Or, you may simply need to change the product in the field to fix a bug, adapt to a new or changing standard, or add functions to make your product more useful.

  Making changes that haven't been completely tested in the original design carry the risk that you may not be able to implement them because of insufficient logic or routing problems brought on by pin fixing. The greater the change, the greater the risk that you may not be able to implement the new design in the old hardware. Although many circuit designs accommodate unplanned circuit changes without difficulty, there is still some risk that you will be unable to make the change.

Reprogramming in the field

  You can reprogram the devices in the field using one of two basic methods. The first method is to connect to the pc board's programming pins with a cable that connects to a PC or other system used to externally reprogram the device. This method requires more effort on the part of the person performing the reprogramming. It's easy for field-service personnel but probably isn't appropriate for most end users.

  The other method of reprogramming in the field is to build the necessary reprogramming circuitry right on the pc board. The manufacturers of ISP devices typically offer application notes to help you design in the reprogramming circuitry. The circuits typically require a microcontroller and a few interface chips. The data itself can come from a variety of sources, including nonvolatile memory, a modem, or a computer. If you use the ISP device in a system that already has a µP, reprogramming may not require any additional hardware.