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Synopsys has entered the emulation-equipment market with Arkos, a system that offers hardware emulation, cycle-based simulation acceleration, and cosimulation. Using a proprietary custom processor architecture, Arkos verifies chips with as many as 4 million ASIC gates. By using a custom chip, Synopsys eliminates design partitioning and routing across many FPGAs, typical in some other emulation systems. The company claims that Arkos lets you compile a 1 million-gate design in four hours, 100 times faster than many current FPGA-based machines. This compilation speed is important, because Arkos now lacks an incremental-recompile feature.
The system provides node visibility, allowing complete probe access to your design, and a built-in logic analyzer with as many as 32,000 probes and up to 128,000-trace depth, depending on the number of probes you configure. You use Arkos with a target system board for emulating a design prototype, with behavioral or C-code stimulus for system emulation, or with a synthesized testbench.
You can also use Arkos as an accelerator for Synopsys’ new Cyclone cycle-based simulator. Cyclone lets you directly simulate Verilog and VHDL RTL code without first synthesizing a design to a gate-level or Boolean description. This feature saves overall simulation time and minimizes host-memory requirements. The simulator accelerates testbenches, memories, and control-logic and datapath portions of a chip. According to Synopsys, this feature yields a 20- to 70-times faster design simulation than event-driven simulators can provide. The company designed Cyclone to work with Synopsys-style synthesis coding. Being cycle-based, Cyclone works on synchronous designs; however, the tool supports multiple clocks along with multiphase, multifrequency, and gated clocks. You can also use Cyclone on multiple-logic-state designs, from two-state for maximum simulation speed through four-state for higher resolution. Cyclone and Arkos together provide 1-MHz simulation.
Arkos runs on a Sun workstation at 500 kHz to 5 MHz. Prices range from $425,000 for a system with approximately a 300,000-gate capacity to $1.75 million for a system handling 1 million gates. VHDL-compatible Cyclone is available for HP, IBM, and Sun workstations for $60,000. A Verilog version will debut in early 1997. —by Jim Lipman
Synopsys, Mountain View, CA. (415) 962-5000, fax (415) 965-8637, http://www.synopsys.com.
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