Out in Front

Behavioral-synthesis tool speeds chip design

RapidPath, a new tool from Dasys, produces a synthesizable, chip-RTL description from a cycle-accurate behavioral description. The tool works on either Verilog or VHDL and offers a unique feature: After partitioning the design into control logic, datapaths, memory, and random logic, it retains the word-oriented configuration of the datapaths and memory blocks. You then use the best logic- and physical-design tools for each type of block. For example, you can use a logic-synthesis tool to produce a gate-level description of the control and random logic, and you can use architecture-specific compilers for datapaths and memories. A pre-RTL synthesis tool, such as RapidPath, lets you use the best logic block for each tool, resulting in smaller chips and better circuit performance. Another advantage is that memory and datapath compilers output structured blocks, which speeds floorplanning and place-and-route tools.

Most common logic-synthesis tools, in contrast, are bit-oriented, meaning that they treat word-oriented structures, such as datapaths and memories, as random logic. This block "decomposition" during synthesis results in a loss of bit grouping, longer interconnect wiring, longer intrablock delays, higher clock skews, and larger chips. RapidPath quickly performs RTL partitioning and synthesis: In a Delco Electronics benchmark, the tool in 5 minutes compiled 1700 lines of Verilog behavioral code, representing 1 million transistors, 16 datapaths, and six memory blocks, into 12,000 lines of RTL code.

You can use RapidPath on both synchronous and asynchronous designs, including those with multiple clocks and resets. The tool is available now on Hewlett-Packard and Sun platforms for $95,000. Dasys plans to release an automatic-scheduling option for RapidPath in the fourth quarter.—by Jim Lipman

Dasys, Pittsburgh, PA. (412) 761-3878, fax (412) 761-6323.