Out in Front

New low-voltage ASIC libraries are power-stingy

Texas Instruments has announced its 0.18-mm ASIC product line, letting you develop chips operating at voltages as low as 1.8V and supporting clock rates higher than 500 MHz. The offering comprises three libraries: TGC6000 gate array, TEC6000 embedded array, and TSC6000 standard cell. The TGC6000 gate arrays feature as many as 12 million gates on a single chip, six levels of metal interconnect, and a core voltage of 1.8V. You can use I/O pads at 5, 3, or 2.5V and an I/O frequency as high as 2.5 GHz. The TSC6000 family for low-power, high-density applications also uses six metal layers and lets you put as many as 16 million gates on a chip. Core voltage is also 1.8V, and the I/O pads support voltages from 5V to 1.8V. Power dissipation at 1.8V is 0.025 mW/MHz/ gate, about 10 times less than other 0.25- and 0.35-mm technologies.

You can choose from a range of system building blocks for your 0.18-mm ASIC designs. These blocks include asynchronous transfer mode, MPEG, media-access controller, DSP, mP, and mC cores. You can also include high-density memory blocks, including DRAM, SRAM, ROM, and flash, and some analog library cells. TI has already started accepting preliminary gate-array designs and plans to ship prototype gate-array chips in mid-1997. The company plans to accept preliminary standard-cell design starts starting in the second half of 1997.—by Jim Lipman

Texas Instruments, Dallas, TX. (800) 477-8924, http://www.ti.com.