Out in Front

Integrated EDA system eases complex-ASIC design

Viewlogic's new ASIC Innovator, an ASIC-design system for complex chips, incorporates the company's tools along with links to other popular EDA tools. The system provides tools for design tasks from design input through hardware/software codesign, design synthesis, HDL simulation, timing analysis, and design-for-test generation. At the heart of ASIC Innovator are Viewlogic's own EDA tools, including the FusionHDL Verilog/VHDL cosimulator, VCS Verilog simulator (Chronologic, Los Altos, CA), SpeedWave VHDL Simulator (Vantage Analysis Systems, Fremont, CA), Motive timing analyzer (Quad Design, Camarillo, CA), PathBlazer datapath synthesizer (Silerity, Pasadena, CA), and TestGen DFT tools (Sunrise Test Systems, Fremont, CA).

Combining different vendors' tools in a single design flow can lead to interoperability problems. Viewlogic addresses this issue by defining several prevalidated intertool communication processes in ASIC Innovator. Examples include predefined processes between Motive and Synopsys' (Mountain View, CA) Design Compiler for handling timing constraints, and other communication processes between TestGen and Cadence's (San Jose, CA) and Avanti's (Sunnyvale, CA) layout tools for handling scan-chain definition and reordering. ASIC Integrator also has links to Eagle Design Automation's (Beaverton, OR) EagleV hardware/software ASIC-verification tool, and Compass Design Automation's (San Jose, CA) ChipPlanner and High Level Design System's (Santa Clara, CA) Design Planner floorplanners.

ASIC Innovator is available now to beta customers. Price depends on configuration and starts at $80,000.—by Jim Lipman

Viewlogic Systems, Marlborough, MA. (508) 480-0881, fax (508) 480-0882, http://www.viewlogic.com.