Design Features

Postlayout EDA tools lock onto full-chip verification

Jim Lipman, Technical Editor

  During chip design, you perform many design validations. However, the checks that follow final chip placement and routing are, perhaps, the most critical. It is at that point that you can most accurately model final chip performance, including all interconnect wiring parasitics. Emerging postlayout-verification tools and design methodology have increased in scope and complexity, along with the chips on which you use them, and emerging EDA companies are responding with tools that address expanding postlayout verification needs.

  Traditional postlayout verification consists of three tests: a design-rule check (DRC) to confirm that physical layout follows the constraints set by the chip-fabrication process; an electrical-rules check (ERC) that looks for simple problems, such as open nodes and transistor shorts; and a final performance simulation that uses interconnect RC parasitics that are back-annotated from the layout into a timing simulator. But, deep-submicron processes and on-chip clocks of more than 100 MHz require verifications that are more accurate, run faster, and can cover an entire chip—not just a portion of it. Many of today's deep-submicron chips need checking beyond physical design rules and timing delays. Signal integrity (SI), power dissipation, and reliability are also potential problems, due to higher chip density and faster clock rates.

  High-speed chips result in signals that often appear more analog than digital. This situation means that you have to check not only the delay of a signal from Point A to Point B, but also the signal's quality, or integrity, as well. Degraded rise and fall times, ringing, reflections, ground bounce, and VDD degradation are some of the SI problems that occur in chips with clock rates of 40 MHz or higher (Reference 1).

  Power-related problems are also on the rise. These problems include not only a chip's total power dissipation, but also the distribution of power across the chip. Sharp discontinuities in dissipation can result in "hot spots" (local high-temperature areas) that can lead to degraded performance of nearby logic blocks or, for mixed-signal chips, analog circuits. Because most of a chip's power is dynamic, verification tools that estimate power dissipation must take into account input-activity level, using the proper test vectors.

  Long-term reliability due to potential electromigration problems is another issue to consider. Over time, excessive current density in a chip's metal interconnect causes the metal to deteriorate at the point at which the current density is highest, the place with the smallest cross-section. Removing metal atoms from that location decreases the cross-section, causing current density to further increase, and, eventually, the line opens.

  Increasing chip density and speed also cause problems by limiting verification-tool capacity. Design databases for deep-submicron chips can be on the order of tens of gigabytes, much of it a result of parasitic extraction and analysis. This size taxes the storage and memory requirements of most computing platforms.

  To eliminate analysis and detailed extraction on unimportant nets, verification tools need to filter extracted data. These tools also need to operate in an incremental mode, checking changes only when you make modifications after a prior verification. Parasitic RC-reduction software, either as a standalone tool or as part of a verification tool, is available from companies such as Avanti, Epic, Mentor Graphics, Simplex Solutions, and Ultima (Table 1). These tools can help but with a loss of extraction accuracy (Table 2). For your most aggressive designs, you still need to have EDA tools that can help manage a design database and that have the muscle to work on 1 million-plus transistor chips.

The heart of verification

  Before you analyze a postlayout chip file, you have to extract information from the file, which is usually in Graphic Design System II (GDSII) format but may also be in CalTech Intermediate Format (CIF) (see box, "Alphabet soup"). To get parasitic resistance and capacitance, and, ultimately, interconnect-delay information, you need an RC-extraction tool. You can do extraction with a dedicated EDA tool or with one that is part of a tool designed for additional analysis, such as a timing verifier. In addition, to obtain current-flow or power estimation, you need to extract the chip's transistors. You also use the extracted netlist to compare the layout to a logical description (netlist) of the chip, sometimes called the LVS (layout-vs-schematic) check. An LVS verification makes sure that the circuit layout you have is equivalent to the logical circuit representation used to derive the layout.

 Parasitic extraction is a key part of postlayout verification. As fabrication technology shrinks below approximately 0.8 mm, the delays on a chip due to interconnect begin to dominate the intrinsic delays of the driving transistors (Figure 1). Smaller chips mean more complex equivalent-RC circuits for the interconnects between transistors. In the past, you could ignore the resistance of an interconnect wire and just take the overlap capacitance of the wire to either the substrate (ac ground) or another wire to calculate the wire's load.

Deep-submicron technology greatly complicates this task. Wire resistance is now an important parameter because thinner and narrower wires, a by-product of shrinking processes, have more resistance than taller, fatter wires. The higher resistance increases the net's load, thus increasing signal delay and skew. Now, you must perform accurate 3-D capacitance extraction. You need an interconnect wire's width and length to calculate overlap capacitance to the wires above and below the interconnect wire. You also need the interconnect's height (thickness) and distance from other wires on the same layer to compute lateral capacitance. Finally, you need to consider fringe capacitance, which is a component added to overlap capacitance (Figure 2).

  State-of-the-art chip processes are also adding more metal wiring layers. A few years ago, you used just two or three layers. Now, you have as many as five or six layers, which further complicates the parasitic-extraction operation.

  There is a trade-off between 2- and 3-D-parameter extraction: the speed of the extraction process vs the accuracy of the extracted data. True 3-D extraction takes too long to do on an entire chip, so you usually use it only on key areas. Frequency Technology describes a typical extraction methodology as consisting of three phases: a coarse (2-D) extraction tied to routing tools, a refined extraction used to prioritize critical nets, and a high-accuracy (3-D) extraction to examine those nets. What you define as a critical net is also important, but which nets to use is not completely obvious. Naturally, clock-distribution networks, or clock trees, are very important and may need very accurate extraction for high-speed chips. The same situation is true for mP computation engines. However, each chip design has its own definition of what are critical speed paths, and you need to recognize which paths are really critical to best determine where to apply the slower 3-D extractions (see box, "Speeding parasitic extraction").

Pumped-up verification tools

 Many new and established EDA companies now offer faster and better verification tools. Simplex Solutions' Fire & Ice and Thunder & Lightning are examples of a new breed of postlayout EDA tools that combine speed, capacity, and broad verification capability. The Simplex tools perform full-chip, 3-D extraction on 4 million-transistor circuits within 24 hours. Dynamic power verification and signal compliance take another 10 hours per 100 test vectors on the same chip. Fire & Ice is a tool that hierarchically extracts transistor and RC parasitics from a GDSII layout file. The tool calculates interconnect capacitance (including lumped, coupled, and distributed components) and resistance to within 5 to 10% that of measured silicon or that calculated by 3-D field solvers. Fire & Ice extracts area, lateral, and fringing capacitance in the presence of multiple surrounding bodies, increasing the accuracy of SI information.

  Thunder & Lightning provides power-grid, clock-tree, and SI verification. The tool uses vectors from a Verilog file to determine active power dissipation. Thunder & Lightning also supplies power-grid verification, including IR drop for supply-voltage degradation and current density for potential electromigration or power and ground-bounce problems. Together with Fire & Ice, Thunder & Lightning checks signal clock-skew compliance, coupling noise, and reliability analysis. Compliance testing includes rise and fall slew rates, signal glitches, setup and hold violations, and other SI problems.

One interesting variation of an existing type of EDA tool is Compass Design Automation's Laybool, an extension of its VFormal formal verification tool. You use traditional formal verification tools, from companies such as Abstract Hardware (Middlesex, UK), Chrysalis (North Billerica, MA), Compass, and Bell Labs Design Automation (Murray Hill, NJ), to compare different logical representations of a design. Formal verifiers compare RTL, gate-level netlist, or transistor-level netlist representations to determine if they are functionally equivalent. Laybool and VFormal go a step further by extracting the netlist from the layout, deriving the Boolean equivalence from the netlist and comparing the Boolean equivalence to the RTL representation of the same circuit (Figure 4). This capability lets you check whether the physical layout represents the same design you had at RTL.

  As chips become more complex and operate at higher speeds, the EDA-tool capabilities needed to verify the chips also grow. The scope of postlayout-verification tools is increasing in what they can do and the speed at which they run.

  After all the design implementation and verification steps leading to the final place and route, you need to integrate these tools into your design flow to assure that the layout you have does, indeed, represent your starting chip design.

References

1. Lipman, Jim, "EDA tools let you track and control CMOS power dissipation," EDN, Nov 23, 1995, pg 65.
2. Napper, Simon, "Technical White Paper on RC Extraction," Epic Design Technology, Sunnyvale, CA, 1995.

Acknowledgments

Thanks to Michael McSherry of Mentor Graphics, Laurie Stanley of Cadence, Camille Aagard of Tsantes, and Georgia Mazsalek for their help in tracking down data-format acronyms. A special thank you to Gary Smith of Dataquest for his enlightening discussions on verification tools and techniques.

You can reach Technical Editor Jim Lipman at (510) 606-1370, fax (510) 606-1563, e-mail ednlipman@mcimail.com.

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