Design Features

Field-programmable devices

Clive "Max" Maxfield, Intergraph Computer Systems

Field-programmable devices come in a variety of fruity flavors, and more are arriving all the time. . . .

People commonly use the term "ASIC" to refer to gate arrays, standard-cell devices, and full custom ICs, all of which a designer specifies but whose final construction is in the hands of a device vendor. However, in its more generic usage, "ASIC" also encompasses those families of components known as "field-programmable devices" (FPDs) (Figure 1). The term "FPD" is the contemporary name for any IC that a user can customize in the field. That is, users having access to the appropriate EDA-software utilities and associated physical-device programming tools can customize an FPD to perform a task or function. Many FPDs exist, and the terminology is always changing. For example, in early 1995, the term "FPD" generally applied only to digital logic, such as simple PLDs (SPLDs), complex PLDs (CPLDs), and FPGAs. By early this year, however, it had grown to encompass field-programmable analog devices (FPADs), and by 1998 it will also include field-programmable mixed-signal devices (FPMSDs).

  The first point-contact transistors arrived on the scene almost 30 years ago. In the early 1950s, bipolar junction transistors (BJTs) superseded the point-contact devices, and MOSFETs appeared 10 years later. Although many references state that PLDs didn't make an appearance until the early 1970s, prototype versions of these devices emerged around 1965. Similar ly, many engineers believe that ASICs are a 1980s technology, but Fairchild in 1967 introduced the Micromosaic, which many believe to be the forerunner of the modern ASIC. Meanwhile, digital FPGAs began to arrive on the scene toward the end of the 1980s; their analog counterparts, FPADs, began to appear in 1994; and mixed-signal versions, FPMSDs, should become available in late 1997 or early 1998.

Programming technologies

  "Programming technology" refers to the physical technique you use to create user-programmable switches for FPDs. The most common such technologies are fusible links, antifuses, EPROM and EEPROM cells and transistors, and SRAM cells. Fusible-link devices are similar to household fuses in that applying an excessive amount of current causes them to change their electrical characteristics in a fairly forthright way. The two main types of fusible-link technologies employ either lateral or vertical fuses. A lateral fuse comprises a tungsten-titanium alloy wire in series with a BJT, which can pass sufficient current to melt the wire. This type of fuse commences as a short circuit and becomes an open circuit when you program it. By comparison, the diode at the base-emitter junction of a BJT forms a vertical fuse. This type of link starts off as an open circuit, because the BJT acts like two back-to-back diodes, thereby preventing current from flowing. However, if you force a sequence of current pulses through the BJT's emitter, an avalanche effect occurs, and the emitter collapses and melts, creating a short circuit.

  As an alternative to fusible links, some FPDs (predominantly, CPLDs and FPGAs) employ antifuse technology. Antifuse links comprise a via of amorphous (noncrystalline) silicon between two layers of metalization. In its unprogrammed state, the amorphous silicon is an insulator with a resistance greater than 1 GV, but the user can program an antifuse link by applying signals of relatively high current (approximately 20 mA) to the device's inputs. The programming signal effectively "grows" a link by changing the insulating amorphous silicon into conducting polysilicon. Both fusible link and antifuse technologies are known as "one-time programmable" (OTP), because once you've programmed them there's no going back or changing your mind (although you can always modify additional unprogrammed links).

  Designers of traditional PLDs (SPLDs) commonly base them on an AND array feeding into an OR array. The most versatile form of this device is a PLA, in which a user controls both the AND and OR arrays (Figure 2). In a PLA, the number of AND functions is independent of the number of inputs, and the number of OR functions is independent of both the number of inputs and the number of AND functions. Also, SPLDs need not have AND input arrays feeding OR output arrays; some devices have two NAND arrays, others have two NOR arrays, and some have a NAND array driving a NOR array. There's even "folded logic," which is based on a single array in which the outputs are fed back into the array to implement sum-of-products expressions.

  Many applications do not require both the AND and OR arrays to be programmable. For example, in PAL devices, the AND array is programmable, and the OR array is predefined. (PAL is a registered trademark of Monolithic Memories Inc.) PLAs are more flexible than PALs, but PALs operate faster, because hard-wired connections take less time to switch than their programmable equivalents. Due to the fact that they are fast and cheap to manufacture, PALs are the most common of all the SPLDs.

  The last of the SPLDs are PROMs, which one can view as a predefined AND array driving a programmable OR array. (In reality, a PROM's internal architecture is more akin to a decoder that is driving a programmable OR array.) People usually think of PROMs as memory devices, in which each address applied to the inputs returns a value programmed into the device. However, PROMs are also PLDs in the classical sense, in that you can use them as hardware truth tables or to implement equations requiring a large number of product terms.

  In addition to their core functionality, SPLDs are available with a variety of additional programmable options, such as tristatable and registered outputs. In the case of registered outputs, many devices allow users to program the type of register required, such as D- or SR-type latches or D-type, T-type, or JK flip-flops. Additionally, many devices let you program their external pins as inputs, outputs, or bidirectionals.

  The concern over fusible link and antifuse technologies—their one-time programmability—is also a concern with PROMs, because the data they store is prone to change, similar to the other SPLDs. All of the components, including the diodes, transistors, and fuses, are created on the surface of a single piece of silicon substrate; however, it can be useful to visualize the device as comprising two distinct strata and then imagine replacing the fusible links with EPROM or EEPROM transistors (Figure 3).

  GAL devices are sophisticated versions of electrically erasable PLDs (EEPLDs) with a few extra bells and whistles. Reprogrammable devices convey advantages over fusible-link and antifuse devices, in that the reprogrammable devices can undergo more rigorous testing at the factory by performing one or more program and erase cycles before shipment to the end user. Also available are in-system-programmable components, which you can program on the pc board.

CPLDs

 
 A CPLD essentially comprises multiple SPLDs on a single chip. You can base the programmable switches on fusible links, antifuses, EPROM transistors, EEPROM transistors, or SRAM cells. Once again, both the logic and the programmable switches are constructed on the same piece of silicon, but it is sometimes easier to visualize them as occupying two distinct strata (Figure 4).

  Some CPLDs based on SRAM programmable switches increase their versatility by letting you use individual blocks of SRAM either as programmable switches or as an actual chunk of memory. The programmable interconnect may contain 100 wires or more, but it would be impractical to feed all of these wires into each SPLD block. Thus, you typically interface the SPLD blocks to the interconnect using a programmable multiplexer (Figure 5).

  One of the advantages of CPLDs is that their regular structures offer reasonably predictable timing. The CPLD market has grown significantly over the last few years, and these devices are finding use in many commercial applications, including the reworking of existing SPLD-based designs into implementations that use fewer chips.

FPGAs

  SPLDs and CPLDs are useful for a variety of tasks, but the structures of their programmable AND and OR planes somewhat limit these devices. At the other end of the spectrum are full-blown ASICs, which include gate arrays, standard-cell, and full-custom devices. These devices are very generic, have fine-grained architectures (at the level of primitive gates and registers), and have capacities of as many as 800,000 gates or more. On the other hand, these devices also have high start-up costs and long design leadtimes. Thus, there is a large gap between SPLDs and CPLDs at the lower end of complexity and ASICs at the high end.

  Toward the end of the 1980s, a new breed of devices, FPGAs, arrived to fill this gap. These devices combined many aspects of gate arrays, such as high density, with those of earlier FPDs, such as field programmability. One differentiating factor is that most FPGAs are coarse-grained, which means that they comprise islands of programmable logic surrounded by programmable interconnect (Figure 6). FPGAs are a little tricky because all of their vendors field their own architectures. Most base the devices on antifuse or SRAM programmable switches.

  
The two predominant architectural approaches to coarse-grained devices are look up-tables (LUTs) and multiplexers. The LUT approach has two main subvariants (Figure 7). Assuming three-input LUTs, one technique involves using a 3-to-8 decoder to select one of eight SRAM cells that contain the required truth-table output values. Alternatively, you can use the SRAM cells to drive a "pyramid" structure of multiplexers that "funnel down" to generate the output. As opposed to LUTs, some FPGA architectures are based almost purely on multiplexers (Figure 8).

  Unfortunately, these coarse-grained FPGA architectures involve several problems. First, interconnect delays are not as predictable as they are with SPLDs and CPLDs. Second, all vendors employ special fitting software to map designs into their devices, which makes it well-nigh impossible to migrate a design from one vendor to another and maintain anything like the same propagation delays. Third, most synthesis-tool makers gear their tools toward fine-grained ASIC architectures. These tools output gate-level netlists, but FPGA fitting tools often do a less than superb job of placing or packing from these netlists. Thus, in addition to relatively poor device-resource usage, these devices make it difficult to estimate realistic propagation delays before routing, which means that you sometimes have to perform a lot of finagling of the design in the downstream portions of the design cycle to make it work.

  However, some design techniques are particularly apt for coarse-grained FPGA architectures, such as the EDIF (Electronic Design Interoperability Format) library of parameterized modules (LPMs) (Reference 1). Also, there is an increasing trend toward fine-grained FPGA architectures, such as QuickLogic's (Santa Clara, CA) pASIC-2 devices, whose cells can act in either a coarse- or a fine-grained fashion, and the CrossFire architecture from Crosspoint Solutions (Milpitas, CA), which employs a super-fine-grained, half-gate basic building block.

FPIDs

  Field-programmable interconnect devices (FPIDs), or field-programmable interconnect chips (FPICs), are a relatively recent breed of components that act as SRAM-based switching matrices (FPIC is a trademark of Aptix Corp, San Jose, CA.) You can dynamically reconfigure these devices, which you use to connect other devices together, in the same way as standard SRAM-based FPGAs. Due to the fact that each FPID may have approximately 1000 pins, a circuit typically requires only a few such devices.

  Aptix has developed an application based on these devices in the form of a reconfigurable development board, which allows you to effectively connect any point on the board to any other point or points. This approach is similar in concept to the breadboards of my youth, except that, instead of playing around with jumper cables with their associated high parasitic inductances and so forth, you use a program running on your computer to generate the FPID-configuration data and download it directly into the development board, thereby allowing you to make changes on the fly.

FPADs and FPMSDs

  One of the more exciting trends in FPDs is their extension into the analog and mixed-signal domains. IMP (San Jose, CA) presented one of the first FPADs to the market in 1994. This device, the IMP 50E10, which IMP calls an electrically programmable analog circuit (EPAC), contains several analog modules, such as analog multiplexers, sample-and-hold amplifiers, and so forth. IMP also provides an easy-to-use programming interface, Analog Magic, which allows you to specify the modules' parameters, such as the gain and offset of amplifiers, and how the modules connect together. IMP plans to release a series of such devices and has recently announced the IMP 50E30, which is designed to monitor, diagnose, and flag out-of-limit analog conditions. This new device is particularly suited to industrial, ATE, process-control, office-equipment, computer-peripheral, and power-control applications. These SRAM-based EPACs let you reprogram them on the fly, but they also have an onboard block of EEPROM that you can load with the configuration data, such that they can adopt a default configuration on power-up. These devices target analog designers, but they are also of interest to digital designers who require a limited amount of analog in their designs. The main problem with EPACs is that they aren't particularly generic, and it's difficult to link the Analog Magic interface to other tools so as to simulate them with other devices.

  Another interesting device, the AL220 programmable analog fuzzy-logic microcontroller from Adaptive Logic (San Jose, CA), is ideal for implementing a variety of control systems. However, the device is not a general-purpose programmable analog device in the wide sense. In fact, the first truly generic FPAD probably won't become available until the end of the year from Motorola (Mesa, AZ). Pilkington glass company (St Helens, UK) created a strategic R&D group called Pilkington Microelectronics (PMEL), which developed a generic programmable analog device, which Motorola has licensed.

  The initial release of this device comprises a four3five-cell array of 20 analog cells, each of which you can configure to act as a high-level function, such as an amplifier, an adder/subtractor, an integrator/differentiator, and so forth. You can individually configure the parameters of each cell, such as the gain of an amplifier, and you can program the way in which all of the cells connect, thereby letting you implement sophisticated analog functions. Additionally, these SRAM-based devices share the same configuration scheme as Motorola's digital FPGAs, and both devices sport an interface bus allowing them to connect to implement two-chip, mixed-signal designs. Motorola has functional silicon for the parts, which will be in beta sampling late this year or early next year. Last but not least, truly general-purpose, single-chip, programmable mixed-signal devices probably won't become available until around 1998, although, just to cover myself, I wouldn't be at all surprised if this occurred sooner...or later.

References

1. Maxfield, Clive "Max," "LPMs: High-level design uses low-level techniques," EDN, May 9, 1996, pg 125.

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