Products

Electronic Design Automation

State-machine software optimizes data-flow support. Version 3.0 of StateCAD, design software for programming ASICs and FPGAs from concurrent state diagrams, supports data flow using complex HDL constructs, including counters, multiplexers, and vector equations. You can drive data-flow logic as a function of state or transition outputs or as independent equations. StateCAD 3.0 runs on Sun workstations and Windows x86 platforms. Windows pricing for VHDL or Verilog starts at $1695; Unix prices start at $2995. Visual Software Solutions, Coral Springs, FL. (954) 346-8890.

Upgrade speeds Spice simulation on Power Macintosh. The Spice simulator in the Electronics Workbench V4.1 Engineer's Pack for the Power Macintosh is 30 times faster than V4.0 and works with 32-bit operating systems. Even on Macs that are not equipped with a PowerPC, the mixed-signal simulator is two times the speed of V4.0. You can export schematic files into PC-based design packages, including OrCAD, Tango, Protel, and Eagle, as well as import and export to other Spice-based simulators. Version 4.1 for the Power Macintosh costs $599. Interactive Image Technologies Ltd, Toronto, ON, Canada. (416) 977-5550.

Software runs physical-design analysis and optimization. SavanSys ad-dresses physical perfor- mance and cost issues for complex electronic system designs at the conceptual phase. The EDA tool lets you define, analyze, and optimize numerous alternative partitioning and packaging solutions for more efficient and timely physical implementation of your design. SavanSys includes graphical editors for partitioning and placement, coupled with advisor modules for analysis of cost, size and weight, reliability, routability, electrical performance, and thermal performance. A floating Unix license starts at $45,000. Savantage Inc, Austin, TX. (512) 305-0050.

Mixed-signal models bolster simulator libraries. >1000 characterized models and >50 generic templates join the libraries of the Saber mixed-technology simulator. Written in the vendor's MAST HDL, the models target automotive, power, and IC/ASIC design applications and include analysis attributes such as dynamic thermal effects, stress measures, and statistical-analysis support. Template additions include Berkeley's short channel IGFET3 models, the EKV micropower analog MOS model, and a family of native Hypermodel interface models for mixed-signal IC/ASIC design. The annual access fee is $5000 and $3600/year thereafter for updates. Analogy, Beaverton, OR. (503) 626-9700.

Unix simulator comes in Windows version. QuickHDL Lite, a Windows version of the QuickHDL simulator, lets you maximize hardware resources by working in a mixed-platform environment. With QuickHDL Lite, you can tackle your portion of an ASIC or FPGA design on a Windows PC before dropping it into a full-system simulation in the Unix environment. To increase performance in Unix environments, an enhanced kernel boosts QuickHDL's performance threefold in gate-level designs. QuickHDL Lite for Windows 95 and NT costs $4995; QuickHDL 5.0 for SunOS, Solaris, HP-UX, and IBM AIX costs $15,500. Mentor Graphics, Wil-sonville, OR. (503) 685-7000.

Software does 458 layout and verification. Version 6.0 of the vendor's L-Edit and L-Edit Pro mask-layout editor and chip-verification system for IC and MEMS design offers 458 DRC and extraction for complex CMOS and bipolar designs. L-Edit supports all angle rotation of instances and even offers a "replace instance" capability. It also includes arc and torus drawing primitives. L-Edit prices start at $1495 for PC and Macintosh platforms and $2995 for Unix systems. Tanner Research Inc, Pasadena, CA. (818) 792-3000.

Graphical-design-entry tool increases code control. Visual HDL 4.0 improves productivity, design analysis, and debugging with open project management and revision control to third-party frame-
works, as well as with refined graphical editors. For instance, the Truth Table editor supports several behavioral models and code styles in simulation and synthesis, including clock and reset, generation of CASE statements, support for a "full_case" synthesis directive, and the ability to control the type of implicit assignments generated by Visual HDL. A floating Unix license costs $30,000; Windows versions cost $12,500. Summit Design Inc, Beaverton, CA. (503) 643-9281.

Enhanced modeling tool offers Windows NT-compatibility. The Foresight systems modeling and simulation tool now runs under Windows NT 3.5. V4.2 of Foresight also adds extensions to system-modeling constructs, such as parameterized user-defined reusable elements. Other enhancements include user-defined minispec procedures, im-proved file I/O routines, and enhanced predefined library elements, including scheduling algorithms (round-robin and nonpre-emptive priority) in the resource elements used to model CPUs and buses in embedded-system models. Foresight V4.2 runs under SunOS, Solaris, HP-UP, and Window NT. Pricing for all platforms starts at $29,500/license. Nu Thena Systems, Mc- Lean, VA. (703) 356-5056.

ASIC libraries optimize speed, die size, and power. High-Density Initiative (HDI) synthesis-optimized-core and pad-cell libraries for three deep-submicron CMOS technologies offer four selectable drive strengths and hand-crafted low-profile cells for simplified routing and smaller die size. Additionally, a noise-isolation scheme cuts power and ground-pin count, and fully integrated analog PLLs reduce system clock-skew problems. The libraries include the 0.35-mm VSC883 (core) and VSC8P38 (pad); the 0.5-mm VSC783 (core) and VSC7P38 (pad); and the 0.6-mm VSC683 (5V) and VSC683L (3.3V) core libraries. The HDI libraries are part of the vendor's Design Integrator environment, which costs $20,000. VLSI Technology Inc, San Jose, CA. (408) 434-3000.

EDA tools tackle manometer-IC designs. EPIC V3.4, a set of tools for analyzing power, timing, and reliability problems in ASIC, structured, and full-custom ICs, provides solutions for 0.35-mm IC designs. These solutions include cross-coupling capacitance extraction, RC reduction, and en-hanced cell-based timing flow. An LEF/DEF interface option for Arcadia, the vendor's RC extraction tool, brings extraction to cell- and block-based designs. All modules in Release 3.4 run on SunOS, Solaris, HP, and IBM platforms. Starting prices are $72,000 (AMPS), $24,400 (Arcadia), $36,400 (PathMill), $60,100 (PowerMill), $132,800 (RailMill), and $44,600 (TimeMill). Epic Design Technology Inc, Sunnyvale, CA. (408) 988-2997.

Tools convert IC layouts. Two IC-layout tools join the vendor's Layout Conversion Environment (LACE). LACE MEGA handles large layouts without manual partitioning, and LACE STAR maintains standard cell-design hierarchy during the compaction process. LACE MEGA has no memory limitations and automatically partitions a layout of several million transistors during the compaction process, compacting the design piece-by-piece. LACE STAR compacts a 200,000-transistor circuit of standard cells as a single block for reuse in new designs. LACE prices start at $250,000 on Sun workstations. Rubicad Corp, San Jose, CA. (408) 995-3334.

Windows program checks cooling. Operating under Windows 95 or NT, Coolit computational fluid dynamics software predicts air flow and heat transfer in packaged electronic equipment. You can set up, compute, and analyze design problems using interactive tools to create, assemble, and package electronic components. Coolit generates finite volume grids auto-
matically, and its solver requires only one parameter—the desired solution accuracy. An introductory license costs $10,000. After December 31, Coolit's annual license will be $12,500. Daat Research Corp, Hanover, NH. (603) 448-1302.

Synthesis tool kit moves designs from schematics to VHDL. The VHDL Discovery Kit converts your FPGA designs from schematics to VHDL-based methodologies. The kit includes a synthesis tool based on the vendor's Galileo engine and Esperan's interactive VHDL training course. Accepting VHDL as input, the PC-based kit offers synthesis and optimization for an FPGA library from Actel, Altera, Lucent, or Xilinx. The VHDL Discovery Kit costs $3495. Exemplar Logic Inc, Alameda, CA. (510) 337-3700.

FPGA-interface kit links VHDL simulators. This interface kit lets you use Mentor Graphics' top-down design environment with QuickLogic's pASIC 1 and pASIC 2 device families. Libraries in the software package integrate design flows between Mentor's tools and the QuickTools FPGA development system. The kit supports Mentor QuickSim II and QuickHDL simulators for VITAL-compliant VHDL simulation. Schematic and VHDL cosimulation is possible with Mentor's QuickHDLPro. The $995 kit comes on CD-ROM and has libraries for Sun and HP workstations. QuickLogic Corp, Santa Clara, CA. (408) 987-2000.

Windows synthesizer works with the MACH 5 CPLDs. With the PLSyn 6.3 Windows-based synthesis program and AMD's MACH 5 CPLD family, you can create high-speed, low-power circuits to be optimized, synthesized, and programmed all in one environment. PLSyn offers device-independent logic synthesis that integrates with schematic capture and minimum/maximum timing simulation. Release 6.3 supports MACH 5's dual-edge biphase clock modes and adds error-handling and -traceability refinements. PLSyn costs $2750. MicroSim Corp, Irvine, CA. (714) 770-3022.

PC-board layout software simplifies design tasks. Advanced PCB 3, a Windows-based pc-board layout system, integrates Protel's EDA/Client design architecture. The updated software adds OLE support and design wizards to guide you through many of the system's most powerful automation processes. System-level features include two high-level macro languages, schematic and pc-board editors, real-time data-base links, and user-customized menus. Advanced PCB 3 costs $2995. For a limited time, an upgrade bundle that includes Advanced PCB 3 and Advanced Route 3 costs $3995. Protel Technology Inc, Santa Clara, CA. (408) 243-8143.

Design tool selects optimal synthesis path. An option for the speedChart graphical design environment for FPGA and ASIC design lets you explore the design space for optimal area and speed during synthesis. The speedExplorer option accepts design and timing constraints as input and automatically generates various styles of functionally equivalent, synthesizable, HDL code and the corresponding Synopsys constraint files. You can analyze the design space with what-if scenarios and the Synopsys Design Compiler. The tool comes in Unix versions and costs $8000. Speed Electronic Inc, Sunnyvale, CA. (408) 328-0950.

Document-management system expands. Version 4 of the AutoEDMS for Windows document, drawing, and image-management system lets you view AutoCAD R.13, MicroStation, CALS IV, and HPGL/2 file formats. AutoEDMS V4 costs $895 for a two-user starter kit. ACS Software Inc, Lomita, CA. (310) 325-3055.