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Design Features |
Termination techniques improve noise margins and reduce signal reflections, but they require that you balance trade-offs among conflicting goals. Understanding your choices and their design impact helps you produce a more reliable and cost-effective design.
Proper signal-line termination in your system design reduces
signal reflection, increases speed and performance, improves signal integrity,
and minimizes intermittent errors. Not all signal lines need termination. If the
lines are short enough, the signal is still rising during the line's
propagation delay. Any reflection becomes part of the rising edge, causing a
pedestal appearance (Figure 1
). With longer lines, the rise of the signal is completed in
less time than does the propagation delay, and reflections appear as an
overshoot and undershoot.
If your design's signal rise time is greater than twice the total propagation delay, you are in a forgiving environment and can forgo special termination efforts; however, if rise time is less than twice the total propagation delay, you must carefully plan and manage termination. Techniques to consider for reducing reflection noise are clamping diodes, series resistor, parallel termination, and ac termination.
You use clamping diodes as virtual terminations at the beginning of the first load as needed and at the end of the last load with the two-thirds rule,which states that the line length to the first load of any net should be at least two-thirds of the total line length. Use dual clamping diodes with one diode connected from output to power supply and the other diode connected from output to ground to clamp both low and high states. You get maximum effectiveness when you place the diodes at the end of the line or at the end of a long, branching-off stub. You can also use clamping diodes to reduce the negative transients that occur due to discontinuities in the middle of a net.
Clamping diodes for termination offer many advantages. They require neither matched impedance nor matching termination resistors. They effectively clamp all signal overshoot to the 1 or 0 logic level and all external noise greater than the 1 or 0 logic levels at the receiving gate or load. They also reduce ringing on a drive line during system check-out.
In contrast to split resistors, clamping diodes cause no substantial increase in power consumption. Also, using a single resistor to ground for termination usually degrades the output high level, resulting in reduced noise immunity. A clamping diode, on the other hand, does not derate the output high level. A series resistor reduces negative transients and increases propagation delays on the net. Resistors reduce the driving device's output-drive capability; clamping diodes do not. Finally, load capacitances on the transmission line combined with a series resistor, make the circuit behave as an RC time constant on the net.
When you use a Schottky barrier diode as a clamping diode, you
use the diode's forward-conduction characteristic to match the line impedance
of the signal path (Figure 2
). The variable conduction curve of the diode permits
you to terminate line impedance from 50 to 150V.
You use series termination with the split-branch topology to
meet a faster timing requirement than clamping diodes can provide (Figure 3
). Series termination provides lower overall power
requirements than do clamping diodes. Reflection at the receiving gate does not
limit the number of lumped loads that you can place at the end of the
series-terminated line, because the source absorbs all the reflection. A series
damping-resistor limits undershoot, overshoot, and ringing.
You can use series damping to extend lines to any length and limit overshoot and undershoot to predetermined amounts, typically, 35 and 12%, respectively. However, series damping reduces dc noise margins and skew times due to RC time-constant behavior on the net.
Some types of parallel termination work well with heavily loaded nets (Reference 1). For example, using a pullup resistor with a load-resistor (RLOAD) connection from output to VCC consumes current from VCC when output is low. Using a pulldown resistor with an RLOAD connection from output to ground, on the other hand, consumes current from VCC when the output is high.
In one type of parallel termination, Thevenin-equivalent, or dual- (split-) termination, resistor RLOAD1 connects from the output to VCC, RLOAD2 connects from output to ground, and RLOAD1 is in series with RLOAD2. This configuration consumes one-half the current of Thevenin-equivalent termination from the output stage. However, this configuration also reduces the noise margin and consumes current from VCC whether outputs are high or low. Using Thevenin-equivalent termination on a three-state bus sets the quiescent line voltage to one-half its usual value.
Another parallel option, ac termination, connects RLOAD between the output and capacitor C, connects C between RLOAD and ground, and places RLOAD in series with C. Connect the capacitance between the termination resistance and ground to avoid the effect of extra capacitance added to the net. This approach consumes no dc at the outputs. If you use this configuration on a three-state bus, you can establish the quiescent voltage on the line at VCC or ground by a high-value pullup or pulldown resistor to the appropriate supply rail. A good value for C is three times the rise time divided by the nominal line impedance.
For memory signals, you should use the clamping diode and the two-thirds rule as your first choice and the series-termination concept second. The choice depends on your application's timing requirements. Clamping diodes typically provide a cleaner signal than series termination, especially when you use them at the first and last loads. For data signals, consider using dual-termination resistors as a first choice and ac termination as a second option. For clock signals, the clamping diode with the two-thirds rule should be the first choice, and ac termination with the two-thirds rule should be the second choice.
Although the objective of termination is to reduce the reflection on a net, designers must choose the best fit for their applications. Each design operates at different frequency ranges and with different parts and timing constraints. Use simulation to understand which technique fits your application.
You can ease your task by starting with just a few simple guidelines. Use the two-thirds rule for line length and load position and maintain 0.5-in. (1-cm) minimum spacing between loads to prevent cluster behavior. Be sure your driver can supply enough current and has sufficient phase margin. You can maximize the number of loads if several factors are in place. First, the driver must have enough current drive to distribute to all the loads and termination. Second, the IC should have a 40 to 458 phase margin to support all loading. If the phase margin of the IC is in that range, the part is much less sensitive to noise than an IC with only 4 to 58 of phase margin. Mismatch creates a lot of reflection noise, so a mismatch situation requires a part that is less sensitive to noise and, therefore, has a high phase margin.
Minimize the number of parts your design needs by increased loading on the same net. This approach reduces the design steps and helps meet budget and time constraints. Also, by improving the waveform shape and reducing the propagation delay, you can partially compensate for the loss of timing and performance due to the degradation in rise time.
To increase noise margin, try to reduce crosstalk by avoiding bundled parallel runs as much as possible between signal layers in the Z direction and signal lines in the X and Y directions. Separate the logic ground from the ground for the high switching-current circuitry. Tie together all grounds at the system ground point so that the ground buses are at the same potential and currents cannot flow in ground loops.
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Author's biography Mai Vu is an analog, digital, and system designer at Harris Computer Systems Corp (Fort Lauderdale, FL). She has a BSEE from the University of Minnesota—Twin Cities (Minneapolis) and an MS in management and technology and an MBA in international business from Nova University (Fort Lauderdale, FL). |
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