Design Ideas

Clock-fail circuit switches to alternate clock

Rick Downs, Dallas Semiconductor, Dallas, TX

A common design need is to detect the presence or absence of a clock signal. In the absence of a clock, it may be necessary to switch to an alternate clock or to at least notify the system that a failure has occurred. The circuit in Figure 1 uses a silicon delay line to anticipate when the next clock cycle is due and makes the flip-flop sample the input clock to verify that a pulse is present. The required delay time is in the range from at least one full clock period to a maximum of 1.5 clock periods.

The minimum acceptable delay for correct operation is greater than one clock period; this delay allows an adequate safety margin for the rise time of the clock edge. The maximum acceptable delay is 1.5 times the input-clock period minus the hold time of the flip-flop, because the flip-flop must take its sample before the next high-to-low clock transition occurs. To ensure correct sampling of the clock during the high time of the next pulse, the input-clock delay time tD is:

t_WH+t_WL<t_D+t_WL,

where tWH is the high time of the clock signal and tWL is the low time of the clock signal. Because a delay line must have an input-pulse width greater than its delay, you must specify the delay line such that t_DELAY<t_WI, where t_DELAY is the delay time of the delay line, and tWI is the smaller of tWH and tWL. It is apparent that tD cannot be equal to tDELAY, because tD must be greater than the entire clock cycle.

The solution is to use a multitap delay line, which has a tDELAY smaller than the minimum input-pulse width but which has enough elements in series (taps) to provide the required tD delay time. For a clock with 50% duty cycle,

tWH=tWL=tWI,

so tD must be greater than 2tDELAY. The third tap of a multitap delay line would thus be a good choice for a clock with 50% duty cycle. You may need more stages if the clock is very asymmetrical.

In all cases, the clock-fail input flag sets within half a clock period of the missing edge (plus the propagation delay of the flip-flop itself). When the clock is restored, a latency period equal to the delay time exists before the flip-flop resets. The circuit in Figure 1 assumes a 20-MHz clock with 50% duty cycle. Thus,

tWH=tWL=tWI=25 nsec.

A DS1000-20 delay line with 20-nsec delay per tap meets the criteria described above, and the use of the third tap provides sampling at the correct time.

This circuit assumes that the clock input reverts to a low level when the clock fails. If the clock is known to fail high, then you can use a different delay-line tap to sample the clock for low levels. With the conditions stated earlier, use of the fourth tap of the DS1000-20 provides the correct sampling delay for the low period of the clock signal. If the failure state of the clock is unknown, then you can combine both approaches (Figure 2). The clock-failure output flag in Figure 2 automatically gates an alternate or a backup clock signal into the system when the main clock fails. The NOR gates provide a multiplexing function; you could use an integrated multiplexer, such as a 74F153, as well. (DI #1938)