| Out in Front |
Specs of 550 MHz, 35 SPECint95, and 60 SPECfp95 are the performance numbers Digital Semiconductor is claiming for its new 21264 Alpha architecture. The 15.2-million-transistor 21264 maintains binary compatibility with its predecessor, the 21164, but Digital’s designers added a wealth of instructions and performance-boosting circuitry.
The 21264 can send as many as four instructions through its pipelines using the combined technologies of out-of-order (OOO) execution with dual queues, register renaming, four integer pipelines, and two floating-point pipelines. The integer and floating-point OOO queues contain 20 and 15 entries, respectively.
Digital designed the 21264’s branch-prediction mechanism to be approximately twice as good as the 21164. The company expects only seven to 10 mispredictions per 1000 when the mP tests the most difficult parts of the SPEC suite. To meet this goal, the mP uses local- and global-history caches. A branch-predictor cache on the 21264 stores almost 8 kbytes of pattern information, an order of magnitude more than that on the 21164. Additional predictor circuitry dynamically determines which method, the local or global, produces the best result. A misprediction of the local and global predictors results in a one- and an eight-cycle bubble, respectively, at 2 nsec per cycle.
To quickly feed the processor, the 21264 has separate system and cache buses, unlike the 21164. The cache bus can feed the 64-kbyte instruction or 64-kbyte data cache at a peak rate of 4 Gbytes/sec, and the system bus can operate as fast as 2 Gbytes/sec. To support the mP’s OOO execution, the bus-interface unit handles as many as 16 pending off-chip memory references. The level-two cache can use high-speed SRAMs with special transceiver/receiver loops or standard Pentium-style PBSRAMs for lower cost systems. Digital also plans to announce a chip set for handling memory control and other system functions. The chip set supports single- or dual-processor designs and as many as two PCI buses.
The 21264 also has special multimedia instructions, including one that supports full-speed MPEG 2 encoding. The video-encoding instruction is similar to the one that Sun’s UltraSPARC Visual Instruction Set (VIS) uses. Alpha also features an on-chip, high-precision PLL that lets you supply a 100- to 125-MHz external clock. Through software control, you can adjust the PLL’s multiplication factor to lower power consumption and, perhaps, develop a system that fits within the Energy Star specification—another first for Alpha.—by Markus Levy
Digital Semiconductor, Hudson, MA. (508) 568-6868.
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