Out in Front

Software checks chip testability at early design stage

Viewlogic has added a new wrinkle to the trend toward bringing more chip design to the beginning of the design process. You use HTX, a testability-checker option of the company’s Sunrise TestGen tool suite, at the RTL of a Verilog-based chip design before synthesizing to a gate level to help determine how testable the implemented design will be. By checking testability before RTL simulation, synthesis, timing analysis, and test insertion, you save valuable design time by spotting potential test problems at the RTL. HTX points out Verilog RTL constructs that make test insertion and automatic test-pattern generation difficult. Examples of such constructs include asynchronous circuitry, hard-to-control resets, and long counter chains.

HTX is compatible with the RTL coding style supported by Synopsys’ Design Compiler. You use HTX as an option to the Sunrise Testability and Analysis Rules checking Tools (START) suite. Prices for the tool start at $35,000.—by Jim Lipman

Viewlogic Systems, Marlborough, MA. (508) 480-0881, fax (508) 480-0882, http://www.viewlogic.com.